diff options
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile')
| -rwxr-xr-x | src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile | 4603 |
1 files changed, 2891 insertions, 1712 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index bdc2e1e0c..5768a4397 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,8 +1,27 @@ -#-- $Id: cen_ddrphy.initfile,v 1.9 2012/06/28 00:48:44 mwuu Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.19 2012/12/12 20:46:54 mwuu Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.19|mwuu |12/12/12|Commented out settings for SIM, changed attribute +# | | |to CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE +#-- 1.18|mwuu |12/03/12|Changed DP18_PLL_CONFIG1 VCO setting +#-- 1.17|mwuu |11/30/12|Changed DP18_PLL_CONFIG0/1 registers & +# | | |DP18_IO_TX_CONFIG0 INTERP_SIG_SLEW field +#-- 1.16|mwuu |11/28/12|Changed ADR TSYS to 0x70 and DP18 TSYS to 0x6B. +# | | |Changed ADR_PLL_VREG_CONFIG0/1 registers. +#-- 1.15|mwuu |11/19/12|Updated TSYS_WR ADR+DP18 with slow process numbers +#-- 1.14|mwuu |11/13/12|Fixed define of Swizzle check, was wrong before. +#-- 1.13|mwuu |11/09/12|Updated SI settings from Paul, new attributes. +# Added dqs swizzle for Glacier0. Added TSYS settings based on freq. +# Changed FW_WR_RD to match DD0 setting. Changed ABORT_ON_CAL_ERR to be +# default. Divided up ADR blocks into ADDR, CNTL, CLK, SPCKE. Added FFE +# settings for drv_imp_dq_dqs. Changed PLL_TUNEMDIV to be same as DD0. +#-- 1.12|bwieman |10/08/12|attempt to restore +#-- 1.11|bellows |10/08/12|moved inifiles to scom sub directory +#-- 1.10|mwuu |08/15/12|Removed bit_disable settings, to be set in FN. +# Cleaned up the settings for sim. Added DIMM functional attribute, +# FIR unmask scom, PC_RESET register #-- 1.9 |mwuu |06/27/12|Added SYS to IS_SIMULATION attribute #-- 1.8 |mwuu |06/18/12|Changed to use spares based on DIMM_TYPE, also # changed FW_RD_WR field to use AL, CL instead of hardcoded value @@ -26,22 +45,17 @@ #--Master list of variables that can be used in this file is at: #--<Attribute Definition Location> -# 5/07/12 Switched to using ENUM values for many attributes -# 5/04/12 Temp workaround for MSS_FREQ and MSS_VOLT -# 4/11/12 Fixed address for DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0 -# started adding expressions for this register, but need bad_bit_mask -# changed -# 4/6/12 Made initfile similar to dial settings for misc registers(PLL,etc.) -# 3/29/12 Added DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0 and -# DPHY01_DDRPHY_DP18_DQSCLK_OFFSET settings for SIM. - SyntaxVersion = 1 -# Jan 15th? SIM uses type 1C 4Rx8/port CDIMM first config -# Jan 31st 1B ISDIMM DDR3 4 DIMMS (1 per port) -# Feb 15 Initfile delivered to Firmware -# interim date some other configs, maybe LR DIMM -# May 15 final initfile complete all configs +# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +# !! data fields are right aligned !! +# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +# +# SIM uses type 1B CDIMM, 2Rx8/drop, dual drop, 1600 +# +# 0 = false, anything else = true +# +# need to figure out GPO, WLO, RLO... #-- ----------------------------------------------------------------------------- #-- ----------------------------------------------------------------------------- @@ -60,23 +74,20 @@ define CEN = TGT1; # parent Centaur # short test for simulation define def_is_sim = (SYS.ATTR_IS_SIMULATION == 1) ; -# TSYS_WRCLK !!NOTE: different depending on EC level -define def_ADR32_TSYS_WRCLK = 0x60 ; -define def_DP18_TSYS_WRCLK = 0x60 ; +# FAST_SIM_PER_CNTR for periodic calibrations +define def_FAST_SIM_PC = 1 ; -# for real HW uncomment, !!FIX once ATTR_EFF_DIMM_SPARE available +# for real HW uncomment, !!FIX once ATTR_EFF_DIMM_SPARE available [2][4][4] port, dimm, rank define def_has_spare = (ATTR_EFF_DIMM_TYPE == 0) ; # CDIMM define def_no_spare = (ATTR_EFF_DIMM_TYPE != 0) ; # others, ISDIMMs, LRDIMM, etc. -#define def_no_spare = (SYS.ATTR_IS_SIMULATION==1); -#define def_has_spare = (SYS.ATTR_IS_SIMULATION==0); -# ports 0,1 must have dimms with ranks to be valid -define def_valid_p0 = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] > 0) || (ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] > 0)) ; -define def_valid_p1 = ((ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] > 0) || (ATTR_EFF_NUM_RANKS_PER_DIMM[1][1] > 0)) ; +# ports 0,1 must have functional dimms to be valid +define def_valid_p0 = (ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR >> 4); +define def_valid_p1 = (ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR & 0x0F); # short test for MBA01 or MBA23 define def_is_mba01 = (ATTR_CHIP_UNIT_POS == 0) ; # MBA01 -define def_is_mba23 = (ATTR_CHIP_UNIT_POS == 1) ; # MBA01 +define def_is_mba23 = (ATTR_CHIP_UNIT_POS == 1) ; # MBA23 # Port 0 valid rank pair[0:3]_p0 # PRIMARY RANK GROUP @@ -122,24 +133,6 @@ define def_val_qrg1_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP1[1] != ENUM_ATTR_EFF_QU define def_val_qrg2_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP2[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 define def_val_qrg3_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP3[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# bitwise | is not working -# -# ena_rank_pair[0:3]_p0 -#define def_val_rp0_3_p0 = def_val_rp0_p0 << 3 | def_val_rp1_p0 << 2 | def_val_rp2_p0 << 1 | def_val_rp3_p0 ; -# 60 , def_val_rp0_p0 , any ; # enable rank pair 0 -# 61 , def_val_rp1_p0 , any ; # enable rank pair 1 -# 62 , def_val_rp2_p0 , any ; # enable rank pair 2 -# 63 , def_val_rp3_p0 , any ; # enable rank pair 3 -# 60:63 , def_val_rp0_3_p0, any ; # enable rank pair0:3 on port 0 -# -# ena_rank_pair[0:3]_p1 -#define def_ena_rp0_3_p1 = def_ena_rp0_p1 << 3 | def_ena_rp1_p1 << 2 | def_ena_rp2_p1 << 1 | def_ena_rp3_p1 ; -# 60 , def_ena_rp0_p1 , any ; # enable rank pair 0 -# 61 , def_ena_rp1_p1 , any ; # enable rank pair 1 -# 62 , def_ena_rp2_p1 , any ; # enable rank pair 2 -# 63 , def_ena_rp3_p1 , any ; # enable rank pair 3 -# 60:63 , def_ena_rp0_3_p1, any ; # enable rank pair0:3 on port 1 - # shorter test for DRAM gen #define def_is_empty = (ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_EMPTY) ; # EMPTY, no dram? define def_is_ddr3 = (ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ; # DDR3 = 1 @@ -163,36 +156,107 @@ define def_is_bl8 = (ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_BL8) ; # burst leng #define def_is_bl_otf = (ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_OTF) ; # burst length on the fly = (1) #define def_is_bl4 = (ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_BL4) ; # burst length 4 = (2) +# shorter test for Centaur receiver impedance DQ / DQS +define def_cri_dqs_ohm15_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15) ; # OHM15 = 0x0F (15) +define def_cri_dqs_ohm20_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20) ; # OHM20 = 0x14 (20) +define def_cri_dqs_ohm30_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30) ; # OHM30 = 0x1E (30) +define def_cri_dqs_ohm40_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40) ; # OHM40 = 0x28 (40) +define def_cri_dqs_ohm48_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48) ; # OHM48 = 0x30 (48) +define def_cri_dqs_ohm60_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60) ; # OHM60 = 0x3C (60) +define def_cri_dqs_ohm80_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80) ; # OHM80 = 0x50 (80) +define def_cri_dqs_ohm120_p0= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120) ; # OHM120 = 0x78 (120) +define def_cri_dqs_ohm160_p0= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160) ; # OHM160 = 0xA0 (160) +define def_cri_dqs_ohm240_p0= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240) ; # OHM240 = 0xF0 (240) + +define def_cri_dqs_ohm15_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15) ; # OHM15 = 0x0F (15) +define def_cri_dqs_ohm20_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20) ; # OHM20 = 0x14 (20) +define def_cri_dqs_ohm30_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30) ; # OHM30 = 0x1E (30) +define def_cri_dqs_ohm40_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40) ; # OHM40 = 0x28 (40) +define def_cri_dqs_ohm48_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48) ; # OHM48 = 0x30 (48) +define def_cri_dqs_ohm60_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60) ; # OHM60 = 0x3C (60) +define def_cri_dqs_ohm80_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80) ; # OHM80 = 0x50 (80) +define def_cri_dqs_ohm120_p1= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120) ; # OHM120 = 0x78 (120) +define def_cri_dqs_ohm160_p1= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160) ; # OHM160 = 0xA0 (160) +define def_cri_dqs_ohm240_p1= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240) ; # OHM240 = 0xF0 (240) + # shorter test for Centaur driver impedance DQ / DQS -define def_cdi_dqs_ohm24 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24) ; # OHM24 = 0x18 (24) -define def_cdi_dqs_ohm30 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_dqs_ohm34 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34) ; # OHM34 = 0x22 (34) -define def_cdi_dqs_ohm40 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40) ; # OHM40 = 0x28 (40) - -# shorter test for Centaur driver impedance command -define def_cdi_cmd_ohm15 = (ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_cmd_ohm20 = (ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_cmd_ohm30 = (ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_cmd_ohm40 = (ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM40) ; # OHM40 = 0x28 (40) - -# shorter test for Centaur driver impedance control -define def_cdi_ctl_ohm15 = (ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_ctl_ohm20 = (ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_ctl_ohm30 = (ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_ctl_ohm40 = (ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) +define def_cdi_dqs_ohm24_p0 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0) ; # OHM24 = 0x18 (24) + +define def_cdi_dqs_ohm30_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120)) ; # OHM30 = 0x1E (30) + +define def_cdi_dqs_ohm34_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120)) ; # OHM34 = 0x22 (34) + +define def_cdi_dqs_ohm40_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; # OHM40 = 0x28 (40) + +define def_cdi_dqs_ohm24_p1 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0) ; # OHM24 = 0x18 (24) + +define def_cdi_dqs_ohm30_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120)) ; # OHM30 = 0x1E (30) + +define def_cdi_dqs_ohm34_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120)) ; # OHM34 = 0x22 (34) + +define def_cdi_dqs_ohm40_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; # OHM40 = 0x28 (40) + +# shorter test for number of FFE slices to enable in TX_CONFIG register +define def_ffe1_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480)) ; + +define def_ffe2_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240)) ; + +define def_ffe3_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160)) ; + +define def_ffe4_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; + +define def_ffe1_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480)) ; + +define def_ffe2_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240)) ; + +define def_ffe3_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160)) ; + +define def_ffe4_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; + +# shorter test for Centaur driver impedance command/address (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) +define def_cdi_addr_ohm15_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_addr_ohm20_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_addr_ohm30_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_addr_ohm40_p0= (ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) + +define def_cdi_addr_ohm15_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_addr_ohm20_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_addr_ohm30_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_addr_ohm40_p1= (ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) + +# shorter test for Centaur driver impedance control (CKE0:1, CKE4:5, ODT0:3, CSN0:7) +define def_cdi_ctl_ohm15_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_ctl_ohm20_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_ctl_ohm30_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_ctl_ohm40_p0 = (ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) + +define def_cdi_ctl_ohm15_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_ctl_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_ctl_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_ctl_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) + +# shorter test for Centaur driver impedance clocks (CLK0:3) +define def_cdi_clk_ohm15_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_clk_ohm20_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_clk_ohm30_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_clk_ohm40_p0 = (ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) + +define def_cdi_clk_ohm15_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_clk_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_clk_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_clk_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) + +# shorter test for Centaur driver impedance spare clocks (CKE2:3, CKE6:7) +define def_cdi_spcke_ohm15_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_spcke_ohm20_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_spcke_ohm30_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_spcke_ohm40_p0 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) + +define def_cdi_spcke_ohm15_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) +define def_cdi_spcke_ohm20_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) +define def_cdi_spcke_ohm30_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) +define def_cdi_spcke_ohm40_p1 = (ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) -# shorter test for Centaur receiver impedance DQ / DQS -define def_cri_dqs_ohm15 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15) ; # OHM15 = 0x0F (15) -define def_cri_dqs_ohm20 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20) ; # OHM20 = 0x14 (20) -define def_cri_dqs_ohm30 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30) ; # OHM30 = 0x1E (30) -define def_cri_dqs_ohm40 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40) ; # OHM40 = 0x28 (40) -define def_cri_dqs_ohm48 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48) ; # OHM48 = 0x30 (48) -define def_cri_dqs_ohm60 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60) ; # OHM60 = 0x3C (60) -define def_cri_dqs_ohm120 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120) ; # OHM120 = 0x78 (120) -#ddr4? 80 160 240 -#define def_cri_dqs_ohm80 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80) ; # OHM80 = 0x50 (80) -#define def_cri_dqs_ohm160 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160) ; # OHM160 = 0xA0 (160) -#define def_cri_dqs_ohm240 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240) ; # OHM240 = 0xF0 (240) # SIMPLIFY # ================================================================================ @@ -218,6 +282,9 @@ define def_tODTL_DDR4 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_A define def_p2p_jitter = 2600 ; # DQS peak to peak jitter in ps define def_dqs_offset = (11 + ((def_p2p_jitter * CEN.ATTR_MSS_FREQ) / 4000000)) ; +# define for glacier1(1), glacier2=normal(0) +define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)) ; + #--------------------------------------------------------------------------------- # ===================================================================================================== @@ -247,45 +314,47 @@ define def_dqs_offset = (11 + ((def_p2p_jitter * CEN.ATTR_MSS_FREQ) / 4000000)) # DPHY01.DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 = 0x8020 # DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0 = 0x8020 # DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 = 0x0010 - -# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# DPHY01 PC IO PVT N/P FET Driver Control !! need to set this? -# -# set to 0x0008, then 0x0000 -# -# [01:23] [0:1] -# DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 0x8000c0140301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG20_L2(0:12) -# -# 48:52 0 PVTP RW PFET Driver PVTP value to send to all output drivers when PVT_OVERRIDE is set. -# 53:57 0 PVTN RW NFET Driver PVTN value to send to all output drivers when PVT_OVERRIDE is set. -# 58 0 PVT_OVERRIDE RW '1'b - All drivers are updated with the PVTP and PVTN values in this register imeadiately. -# '0'b - All drivers are updated with the PVTP and PVTN values from the impedance calibration state machine. -# 59 0 ENABLE_ZCAL RW '1'b - Enable Impedance Controller. -# '0'b - Disable Impedance Controller. -# 60 0 RESET_ZCAL RW Reset Impedance Controller. The value of this field is driven to the zcntl_reset_o -# output for optional connection to the reset of an Impedance Controller. -# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # --------------------------------------------------------------------------------------- # Pervasive FIR registers # +# Error mask register where (Action0, Action1, Mask) = Action Select; +# +# (0,0,x) = No Error reported +# (0,1,0) = Recoverable Error +# (1,0,0) = Checkstop Error +# (1,1,0) = Local Core Checkstop +# (x,x,1) = MASKED +# +# PHY01_DDRPHY_FIR_REG default=0 0x800200900301143f +# PHY01_DDRPHY_FIR_MASK_REG default=0 0x800200930301143f # PHY01_DDRPHY_FIR_ACTION0_REG default=0 0x800200960301143f # PHY01_DDRPHY_FIR_ACTION1_REG default=0 0x800200970301143f -# PHY01_DDRPHY_FIR_MASK_REG default=0 0x800200930301143f -# PHY01_DDRPHY_FIR_REG default=0 0x800200900301143f # PHY01_DDRPHY_FIR_WOF_REG default=0 0x800200980301143f # +# PHY01_DDRPHY_FIR_MASK_REG default=0 0x800200930301143f +# scomx.fir0.fir_mask_lt +scom 0x800200930301143f { # covers both ports + # 48:52 = port0 { FSM, parity, cal, FSM recover, parity recover } + # 53 = port 0/1 FIR parity recover error + # 56:60 = port1 { FSM, parity, cal, FSM recover, parity recover } + scom_data , expr ; + # fix for DD1 mask all PHY FIR bits. + 0x000000000000FFFF , (CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE) ; + 0x0000000000000000 , any ; +} # --------------------------------------------------------------------------------------- # PC Config0 # # ddr3=0x0000, ddr4=0x1202 # !! set in ddr_phy_reset # -# DPHY01.DDRPHY_PC_CONFIG0_P[0:1] from (alias spydef) -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG12_L2 0x00C 0x8000c00c0301143f +# DPHY01.DDRPHY_PC_CONFIG0_P[0:1] 0x00C 0x8000c00c0301143f +# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG12_L2 scom 0x800(0,1)C00C0301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # Protocol, 0=DDR3, 1=DDR4, 2=RLDRAM2 CIO, 4=RLDRAM3 48:51 , 0b0001 , (def_is_ddr4) ; # ATTR_EFF_DRAM_GEN=2=DDR4 48:51 , 0b0000 , (def_not_ddr4) ; # ATTR_EFF_DRAM_GEN=1=DDR3 or 0=empty @@ -296,37 +365,58 @@ scom 0x800(0,1)C00C0301143F { # _P[0:1] 55 , 0b0 , any ; # SysClK 2x Mem Internal CLK 56 , 0b0 , any ; # Rank Override enable 57:59 , 0b000 , any ; # Rank Override value +# DDR4_RD_PREAMBLE_TRAIN ? 60 , 0b0 , any ; # low latency (ERS Mode), 1=force off, 0=auto +# DDR4_BANK_REFRESH ? # 61 , 0b0 , any ; # reserved 62 , 0b1 , (def_is_ddr4) ; # enable DDR4_VLEVEL_BANK_GROUP 62 , 0b0 , (def_not_ddr4) ; # disable for DDR3 -# 63 , 0b0 , any ; # reserved +# DDR4_DQ_LINK_TRAIN ? + 63 , 0b0 , any ; # ZCAL_NOT_CONT (set to continuously int zcal) } -# + # --------------------------------------------------------------------------------------- # PC_CONFIG1 # -# DPHY01.DDRPHY_PC_CONFIG1_P0 from (alias spydef) +# DPHY01.DDRPHY_PC_CONFIG1_P0 scom 0x800(0,1)C00D0301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 - 48:51 , 0b0001 , (def_is_rdimm) ; # RDIMM - 48:51 , 0b0000 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) +# DD0 = PORT_BUFFER_LATENCY + 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM + 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) # # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} - 52:55 , 0b0000 , (def_is_cdimm) ; # CDIMM - 52:55 , 0b0001 , (def_is_rdimm) ; # RDIMM - 52:55 , 0b0010 , (def_is_lrdimm) ; # LRDIMM + 52:55 , 0x0 , (def_is_cdimm) ; # CDIMM + 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM + 52:55 , 0x2 , (def_is_lrdimm) ; # LRDIMM 56 , 0b0 , any ; # MEMCTL_CIC_FAST 57 , 0b0 , any ; # MEMCTL_CTRN_IGNORE 58 , 0b0 , any ; # DISABLE_MEMCTL_CAL +# Memory Type # # 59:61 , 000=DDR3/DDR4 CDIMM, DDR3 (001=RDIMM, 011=LRDIMM), DDR4 (101=RDIMM, 111=LRDIMM) 59:61 , 0b000 , (def_is_cdimm) ; # CDIMM 59:61 , 0b001 , ((def_is_rdimm) && (def_is_ddr3)) ; # DDR3 RDIMM 59:61 , 0b011 , ((def_is_lrdimm) && (def_is_ddr3)) ; # DDR3 LRDIMM 59:61 , 0b101 , ((def_is_rdimm) && (def_is_ddr4)) ; # DDR4 RDIMM 59:61 , 0b111 , ((def_is_lrdimm) && (def_is_ddr4)) ; # DDR4 LRDIMM -# 62:63 , 0b00 , any ; # reserved - } +# 62 , 0b1 , any ; # DDR4 Latency Chicken SW +# 63 , 0b0 , any ; # Retain_Percal_SW +} + +# --------------------------------------------------------------------------------------- +# PC Resets register default=0xC000 +# +# This register provides the capability to initiate resets in the hard cores. +# +# DPHY01_DDRPHY_PC_RESETS_P0 0x8000c00e0301143f +scom 0x800(0,1)C00E0301143F { # Port[0:1] + bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved + 48 , 0b1 ; # PLL_RESET (all PLL's) + 49 , 0b1 ; # SYSCLK_RESET (all logic in sysclk domain) +# 50:63 , 0x0000 ; # reserved +} # --------------------------------------------------------------------------------------- # ADR PLL VREG Config0 default=0 !! register definition for TUNEF not correct for '111b'? @@ -342,14 +432,32 @@ scom 0x800(0,1)C00D0301143F { #scom 0x8000(80,84)300301143F { # PHY01 Port0 ADR32S[0:1] scom 0x800(0,1)BC300301143F { # PHY01 Port[0:1] broadcast ADR32S[0:1] bits , scom_data , expr ; -# # 0b111 000 111011 00 00 20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low - 48:63 , 0xE3B0 , ((CEN.ATTR_MSS_FREQ/2) < 600) ; # 300-599.9 MHz, < 1200 MT/s +# 0:47 , 0x000000000000, any ; # reserved +# # 0b110 100 101011 00 00 22.22uA, gain 5, SE(3pF, 24pF, 800 ohms), VCO=low, PLLXTR +# 48:59 , 0xD2B , (def_is_sim) ; # same as DD0 -# # 0b010 000 111000 00 00 40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low - 48:63 , 0x4380 , ((CEN.ATTR_MSS_FREQ/2) < 1000) ; # 600-999.9 MHz, 1200-2000 MT/s +# # 0b111 000 111011 00 00 20uA, gain 1, SE(3pF, 24pF, 200 ohms), VCO=low +# 48:63 , 0xE3B0 , ((CEN.ATTR_MSS_FREQ/2) < 600) ; # 300-599.9 MHz, < 1200 MT/s + +# # 0b010 000 111000 00 00 40uA, gain 1, SE(2pF, 16pF, 200 ohms), VCO=low +# 48:63 , 0x4380 , ((CEN.ATTR_MSS_FREQ/2) < 1000) ; # 600-999.9 MHz, 1200-2000 MT/s + +# # 0b100 011 111011 01 00 28.57uA, gain 4, SE(3pF, 24pF, 200 ohms), VCO=high +# 48:63 , 0x8FB4 , ((CEN.ATTR_MSS_FREQ/2) >= 1000) ; # 1000-1066 MHz, >=2000 MT/s + +# new setting from Joe Iadanza 11/30 +# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) + 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ < 1200) ; # < 600 MHz, 1200 MT/s + +# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) + 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ < 1460) ; # < 730 MHz, < 1460 MT/s + +# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) + 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ > 1459) ; # >= 730 MHz, >=1460 MT/s + + 60:63 , 0x4 , (def_is_ddr4) ; # VCO = high for DDR4 + 60:63 , 0x0 , any ; # VCO = low for DDR3 -# # 0b100 011 111011 01 00 28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high - 48:63 , 0x8FB4 , ((CEN.ATTR_MSS_FREQ/2) >= 1000) ; # 1000-1066 MHz, >=2000 MT/s } # --------------------------------------------------------------------------------------- @@ -360,46 +468,50 @@ scom 0x800(0,1)BC300301143F { # PHY01 Port[0:1] broadcast ADR32S[0:1] # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.P_REG_31_L2 #scom 0x8000(80,84)310301143f { # PHY01 Port0 ADR32S[0:1] scom 0x800(0,1)BC310301143f { # PHY01 Port[0:1] broadcast ADR32S[0:1] - bits , scom_data , expr ; + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # PLL_TUNETDIV(0:2) PLLTESTOUT (000=logic 1, 001=MDIVOUT div by 64, 01x=MDIVOUT div by 1, 1xx=dsabled, logic 0) - 48:50 , 0b100 , any ; # disabled +# 48:50 , 0b100 , (def_is_sim) ; # disabled, for SIM + 48:50 , 0b111 , any ; # disabled, was '100' - # !! PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value" -# 51:52 , 0b00 , any ; # workaround? - 51:52 , 0b00 , ((CEN.ATTR_MSS_FREQ/2) < 800) ; # < 1600 MT/s - 51:52 , 0b01 , ((CEN.ATTR_MSS_FREQ/2) >= 800) ; # >=1600 MT/s + # PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value(00)" + 51:52 , 0b00 , any ; # same as DD0 +# 51:52 , 0b00 , ((CEN.ATTR_MSS_FREQ/2) < 800) ; # < 1600 MT/s +# 51:52 , 0b01 , ((CEN.ATTR_MSS_FREQ/2) >= 800) ; # >=1600 MT/s # PLL_TUNEATST (0=HiZ, 1=CMFB internal) - HiZ, "for all frequencies 0 is required" - 53 , 0b0 , any ; # HiZ + 53 , 0b0 , any ; # HiZ # VREG_RANGE(0:1) (00=1.50V, 01=1.35V, 11=1.20V) - # !! Need to change if using 1.25V since overlap occurs! - 54:55 , 0b11 , CEN.ATTR_MSS_VOLT <= 1271 ; # set to 1.2V - 54:55 , 0b01 , ((CEN.ATTR_MSS_VOLT > 1271) && (CEN.ATTR_MSS_VOLT <= 1421)) ; # set to 1.35V - 54:55 , 0b00 , CEN.ATTR_MSS_VOLT > 1421 ; # set to 1.5V +# 54:55 , 0b01 , (def_is_sim) ; # set to 1.35 for SIM + 54:55 , 0b11 , (CEN.ATTR_MSS_VOLT <= 1271) ; # set to 1.2V + 54:55 , 0b00 , any ; # set to 1.35V & 1.5V # VREG_VREGSPARE, Extra pins for later expansion. should be put to 0 - 56 , 0b0 , any ; + 56 , 0b0 , any ; # VREG_VCCTUNE(0:1) (00=850mV, 01=855mV, 10=860mV, 11=865mV) -# !recent - 57:58 , 0b00 , (def_is_sim) ; # match dials -# 57:58 , 0b10 , any ; # standard operating point + 57:58 , 0b10 , any ; # standard operating point # INTERP_SIG_SLEW(0:3), Interpolated Signal Slew (PRSTCH pins on ADR16) clk freq -# !! Temp workaround for attribute - 59:62 , 0b0000 , any ; # match dials - 59:62 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 - 59:62 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 - 59:62 , 0b0110 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 - 59:62 , 0b1010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 - 59:62 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 - 59:62 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1013) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 - 59:62 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 933) && (CEN.ATTR_MSS_FREQ <= 1113)) ; # 800 - 59:62 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 933) ; # 666 +# 59:62 , 0b1010 , (def_is_sim) ; # for SIM +# new setting from Joe Iadanza 11/30 + 59:62 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 1200) ; # -1066 + 59:62 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 + 59:62 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 + 59:62 , 0b1100 , (CEN.ATTR_MSS_FREQ > 1732) ; # 1866+ + +# 59:62 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 +# 59:62 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 +# 59:62 , 0b0110 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 +# 59:62 , 0b1010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 +# 59:62 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 +# 59:62 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1013) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 +# 59:62 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 933) && (CEN.ATTR_MSS_FREQ <= 1113)) ; # 800 +# 59:62 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 933) ; # 666 # ANALOG_WRAPON, Wrap Data control to attached ADR16(s)/ADR12(s) - 63 , 0b0 , any ; + 63 , 0b0 , any ; } # --------------------------------------------------------------------------------------- @@ -410,15 +522,33 @@ scom 0x800(0,1)BC310301143f { # PHY01 Port[0:1] broadcast ADR32S[0:1] # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_PLL_CONFIG0_L2 # scom 0x8000(00,04,08,0C,10)760301143f { # CONFIG0_P0_[0:4] scom 0x800(0,1)3C760301143F { # CONFIG0_P[0:1] broadcast [0:4] - bits , scom_data , expr ; - # 0b111 000 111011 00 00 20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low - 48:63 , 0xE3B0 , ((CEN.ATTR_MSS_FREQ/2) < 600) ; # 300-599.9 MHz, < 1200 MT/s + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# # 0b111 000 111011 00 00 20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low +# # 300-599.9 MHz, < 1200 MT/s +# 48:59 , 0xE3B , ((def_is_sim) && (CEN.ATTR_MSS_FREQ < 1200)) ; +# +# # 0b010 000 111000 00 00 40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low +# # 600-999.9 MHz, 1200-2000 MT/s +# 48:59 , 0x438 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ < 2000)) ; +# +# # 0b100 011 111011 01 00 28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high +# # 1000-1066 MHz, >=2000 MT/s +# 48:59 , 0x8FB , ((def_is_sim) && (CEN.ATTR_MSS_FREQ >= 2000)) ; - # 0b010 000 111000 00 00 40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low - 48:63 , 0x4380 , ((CEN.ATTR_MSS_FREQ/2) < 1000) ; # 600-999.9 MHz, 1200-2000 MT/s +# new setting from Joe Iadanza 11/30 +# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) + 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ < 1200) ; # < 600 MHz, 1200 MT/s - # 0b100 011 111011 01 00 28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high - 48:63 , 0x8FB4 , ((CEN.ATTR_MSS_FREQ/2) >= 1000) ; # 1000-1066 MHz, >=2000 MT/s +# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) + 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ < 1460) ; # < 730 MHz, < 1460 MT/s + +# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) + 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ > 1459) ; # >= 730 MHz, >=1460 MT/s + +# 60:63 , 0x0 , (def_is_sim) ; # for SIM + 60:63 , 0x4 , (CEN.ATTR_MSS_FREQ > 1459) ; # VCO = high for >= 730MHz or 1460 MT/s + 60:63 , 0x0 , any ; # VCO = low for < 730MHz } # --------------------------------------------------------------------------------------- @@ -428,37 +558,36 @@ scom 0x800(0,1)3C760301143F { # CONFIG0_P[0:1] broadcast [0:4] # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_PLL_CONFIG1_L2 # scom 0x8000(00,04,08,0C,10)770301143f { # CONFIG1_P0_[0:4] scom 0x800(0,1)3C770301143F { # CONFIG1_P[0:1] broadcast [0:4] - bits , scom_data , expr ; + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # PLL_TUNETDIV(0:2) PLLTESTOUT (all freq 1xx required) - 48:50 , 0b100 , any ; # disabled +# 48:50 , 0b100 , (def_is_sim) ; # disabled + 48:50 , 0b111 , any ; # disabled - # !! PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value" -# 51:52 , 0b00 , any ; # workaround? - 51:52 , 0b00 , ((CEN.ATTR_MSS_FREQ/2) < 800) ; # < 1600 MT/s - 51:52 , 0b01 , ((CEN.ATTR_MSS_FREQ/2) >= 800) ; # >=1600 MT/s + # PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value" +# 51:52 , 0b01 , (def_is_sim) ; # 2 + 51:52 , 0b00 , any ; # 1 # PLL_TUNEATST (0=HiZ, 1=CMFB internal) - HiZ, "for all frequencies 0 is required" - 53 , 0b0 , any ; # HiZ + 53 , 0b0 , any ; # HiZ # VREG_RANGE(0:1) (00=1.50V, 01=1.35V, 11=1.20V) # !! Need to change if using 1.25V since overlap occurs! - 54:55 , 0b11 , CEN.ATTR_MSS_VOLT <= 1271 ; # set to 1.2V - 54:55 , 0b01 , ((CEN.ATTR_MSS_VOLT > 1271) && (CEN.ATTR_MSS_VOLT <= 1421)) ; # set to 1.35V - 54:55 , 0b00 , CEN.ATTR_MSS_VOLT > 1421 ; # set to 1.5V +# 54:55 , 0b01 , (def_is_sim) ; # set to 1.35V for sim + 54:55 , 0b11 , (CEN.ATTR_MSS_VOLT <= 1271) ; # set to 1.2V + 54:55 , 0b00 , any ; # set to 1.35V, & 1.5V # CE0DLTVCCA - 56 , 0b0 , any ; # must be 0 + 56 , 0b0 , any ; # must be 0 # VREG_VCCTUNE(0:1) (00=850mV, 01=855mV, 10=860mV, 11=865mV) -# !recent - 57:58 , 0b00 , (def_is_sim) ; # match dials -# 57:58 , 0b10 , any ; # standard = 860 + 57:58 , 0b10 , any ; # standard = 860 - 59 , 0b0 , any ; # CE0DLTVCCD1, must be 0 - 60 , 0b0 , any ; # CE0DLTVCCD2, must be 0 - 61 , 0b0 , any ; # S0INSDLYTAP, must be 0 - 62 , 0b0 , any ; # S1INSDLYTAP, must be 0 -# 63 , 0b0 , any ; # Reserved + 59 , 0b0 , any ; # CE0DLTVCCD1, must be 0 + 60 , 0b0 , any ; # CE0DLTVCCD2, must be 0 + 61 , 0b0 , any ; # S0INSDLYTAP, must be 0 + 62 , 0b0 , any ; # S1INSDLYTAP, must be 0 +# 63 , 0b0 , any ; # reserved } # freq ranges @@ -487,41 +616,68 @@ scom 0x800(0,1)3C770301143F { # CONFIG1_P[0:1] broadcast [0:4] # CEN.ATTR_MSS_FREQ # ATTR_EFF_CEN_SLEW_RATE_DQ_DQS [0:15] 0=slow, 15=fast # +# FFE=feed forward equalization, DFE=decision feedback equalization +# # [01:23] [0:1][0:4] # DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0 0x075 0x800000750301143f # PHYW.PHYX.GEN_DP#1.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_CONFIG0_L2 #scom 0x8000(00,04,08,0C,10)750301143F { # CONFIG0_P0_[0:4] -scom 0x800(0,1)3C750301143F { # CONFIG0_P[0:1] broadcast [0:4] - bits , scom_data , expr ; +scom 0x80003C750301143F { # CONFIG0_P0 broadcast [0:4] + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + # INTERP_SIG_SLEW for phase rotator +# 48:51 , 0b1100 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 +# 48:51 , 0b0010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 +# 48:51 , 0b1010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 +# 48:51 , 0b0110 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 +# 48:51 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 +# 48:51 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 + +# new setting from Joe Iadanza 11/30 + 48:51 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 1200) ; # 1066 + 48:51 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 + 48:51 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 + 48:51 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 + + # Post Cursor, tap coefficient for FFE, 0=no equalization + 52:55 , 0b0001 , (def_ffe1_p0) ; + 52:55 , 0b0011 , (def_ffe2_p0) ; + 52:55 , 0b0111 , (def_ffe3_p0) ; + 52:55 , 0b1111 , (def_ffe4_p0) ; + 52:55 , 0b0000 , any ; + + # Slew rate set in ddrphy_reset procedure via slew FN call +# 56:59 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 0) ; # SLEW_CTL, slowest +# 60:63 , 0b0000 , any ; # reserved +} + +# DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0 0x075 0x800100750301143f +scom 0x80013C750301143F { # CONFIG0_P1 broadcast [0:4] + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # INTERP_SIG_SLEW for phase rotator - 48:51 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 - 48:51 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 - 48:51 , 0b0110 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 - 48:51 , 0b1010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 - 48:51 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 - 48:51 , 0b1100 , (CEN.ATTR_MSS_FREQ <= 1200) ; # 1066 - - # Post Cursor, tap coefficient for FFE, 0=no equalization, will be taken out for DD1? - 52:55 , 0b0000 , any ; - - # choices... 0=2.83, 1=3.35, 2=4.35, 3=5.16, 4=6.16, 5=6.50 V/ns, 6..F ~180mV/step - 56:59 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 0) ; # SLEW_CTL, slowest - 56:59 , 0b0001 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 1) ; # faster . - 56:59 , 0b0010 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 2) ; # faster .. - 56:59 , 0b0011 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 3) ; # faster ... - 56:59 , 0b0100 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 4) ; # faster .... - 56:59 , 0b0101 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 5) ; # faster ..... - 56:59 , 0b0110 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 6) ; # faster ...... - 56:59 , 0b0111 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 7) ; # faster ....... - 56:59 , 0b1000 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 8) ; # faster ........ - 56:59 , 0b1001 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 9) ; # faster ......... - 56:59 , 0b1010 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 10) ; # faster .......... - 56:59 , 0b1011 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 11) ; # faster ........... - 56:59 , 0b1100 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 12) ; # faster ............ - 56:59 , 0b1101 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 13) ; # faster ............. - 56:59 , 0b1110 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 14) ; # faster .............. - 56:59 , 0b1111 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 15) ; # fastest............... -# 60:63 , 0b0000 , any ; # reserved +# 48:51 , 0b1100 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 +# 48:51 , 0b0010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 +# 48:51 , 0b1010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 +# 48:51 , 0b0110 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 +# 48:51 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 +# 48:51 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 + +# new setting from Joe Iadanza 11/30 + 48:51 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 1200) ; # 1066 + 48:51 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 + 48:51 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 + 48:51 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 + + # Post Cursor, tap coefficient for FFE, 0=no equalization + 52:55 , 0b0001 , (def_ffe1_p1) ; + 52:55 , 0b0011 , (def_ffe2_p1) ; + 52:55 , 0b0111 , (def_ffe3_p1) ; + 52:55 , 0b1111 , (def_ffe4_p1) ; + 52:55 , 0b0000 , any ; + # Slew rate set in ddrphy_reset procedure via slew FN call +# 56:59 , 0b0000 , any ; +# 60:63 , 0b0000 , any ; # reserved } # --------------------------------------------------------------------------------------- @@ -535,7 +691,7 @@ scom 0x800(0,1)3C750301143F { # CONFIG0_P[0:1] broadcast [0:4] # 48:55 = N/P FET slices (0-7), 56:59 = N/P FET FFE slices (0-4) # 2 slices of 480 (FFE) = 1 slice of 240 (non-FFE) # -# for DDR4 where VDDR (POD) +# for DDR4 where VDDR (POD=Pseudo Open Drain) # DDR4 ohms = 1 / ((1 / (total 240 slices / 240)) + (1 / (total 480 slices / 480))) # # for DDR3 VDDR/2 @@ -545,67 +701,106 @@ scom 0x800(0,1)3C750301143F { # CONFIG0_P[0:1] broadcast [0:4] # DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0 0x07A 0x8000007a0301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_NFET_TERM_L2(0:11) #scom 0x8000(00,04,08,0C,10)7A0301143f { # NFET_TERM_P0_[0:4] broadcast -scom 0x800(0,1)3C7A0301143f { # NFET_TERM_P[0:1]_[0:4] broadcast +scom 0x80003C7A0301143f { # NFET_TERM_P0_[0:4] broadcast bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # for DDR3 = 1 ohms # ohm/slices - 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15)) ; # 240/8, 480/0 - 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20)) ; # 240/6, 480/0 - 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48)) ; # 240/2, 480/1 - - 48:59 , 0x03F , ((def_is_ddr3) && (def_cri_dqs_ohm30)) ; # 240/2, 480/4 - 48:59 , 0x01F , ((def_is_ddr3) && (def_cri_dqs_ohm40)) ; # 240/1, 480/4 - 48:59 , 0x00F , ((def_is_ddr3) && (def_cri_dqs_ohm60)) ; # 240/0, 480/4 - 48:59 , 0x007 , ((def_is_ddr3) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm120)) ; # 240/0, 480/2 -# Joe Iadanza's spreadsheet (from Saravana note 3/28/12 11:20A) has this... -# 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30)) ; # 240/4, 480/0 -# 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40)) ; # 240/2, 480/2 -# 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60)) ; # 240/2, 480/0 -# 48:59 , 0x102 , ((def_is_ddr3) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80)) ; # 240/1, 480/1 -# 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120)) ; # 240/1, 480/0 -# -# !! need to find out if supporting POD Mode Termination (DDR4 only?) -# if no, then remove def_is_ddr3 from statements above -# if yes, then leave above statements and remove commented section below. -# -# Note 6) For POD Mode Termination, the slice vector is only applied to the PFET portion of the Driver (High). -# The NFET portion of the Driver uses vector 0,0 for high impedance -# -# 48:59 , 0x03F , ((def_is_ddr4) && (def_cri_dqs_ohm60)) ; # 240/2, 480/4 -# 48:59 , 0x01F , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80)) ; # 240/1, 480/4 -# 48:59 , 0x00F , ((def_is_ddr4) && (def_cri_dqs_ohm120)) ; # 240/0, 480/4 -# 48:59 , 0x007 , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 160)) ; # 240/0, 480/3 -# 48:59 , 0x003 , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 240)) ; # 240/0, 480/2 -# for DDR4 will catch DDR3 & not valid imp - 48:59 , 0x000 , any ; # 240/0, 480/0 +# Joe Iadanza's spreadsheet (from Saravanan note 3/28/12 11:20A) has this... + 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p0)) ; # 240/8, 480/0 + 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p0)) ; # 240/6, 480/0 + 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p0)) ; # 240/4, 480/0 +# 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p0)) ; # 240/3, 480/1 + 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p0)) ; # 240/2, 480/2 + 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p0)) ; # 240/2, 480/1 + 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p0)) ; # 240/2, 480/0 + 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p0)) ; # 240/1, 480/1 + 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p0)) ; # 240/1, 480/0 + 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p0)) ; # 240/0, 480/3 + 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p0)) ; # 240/0, 480/2 + 48:59 , 0x000 , any ; # 240/0, 480/0 +# 60:63 , 0b0000 , any ; # reserved } # DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0 0x07B 0x8000007B0301143f #scom 0x8000(00,04,08,0C,10)7B0301143f { # PFET_TERM_P0_[0:4] -scom 0x800(0,1)3C7B0301143f { # PFET_TERM_P[0:1]_[0:4] broadcast +scom 0x80003C7B0301143f { # PFET_TERM_P0_[0:4] broadcast + bits , scom_data, expr ; +# 0:47 , 0x000000000000, any ; # reserved + # for DDR3 = 1 ohms # ohm/slices + 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p0)) ; # 240/8, 480/0 + 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p0)) ; # 240/6, 480/0 + 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p0)) ; # 240/4, 480/0 + # 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p0)) ; # 240/3, 480/1 + 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p0)) ; # 240/2, 480/2 + 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p0)) ; # 240/2, 480/1 + 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p0)) ; # 240/2, 480/0 + 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p0)) ; # 240/1, 480/1 + 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p0)) ; # 240/1, 480/0 + 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p0)) ; # 240/0, 480/3 + 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p0)) ; # 240/0, 480/2 + # for DDR4 = 2 + # 48:59 , 0x7E6 , ((def_is_ddr4) && (def_cri_dqs_ohm34_p0)) ; # 240/8, 480/2 + 48:59 , 0x7E0 , ((def_is_ddr4) && (def_cri_dqs_ohm40_p0)) ; # 240/8, 480/0 + 48:59 , 0x3C6 , ((def_is_ddr4) && (def_cri_dqs_ohm48_p0)) ; # 240/4, 480/2 + 48:59 , 0x3C0 , ((def_is_ddr4) && (def_cri_dqs_ohm60_p0)) ; # 240/4, 480/0 + 48:59 , 0x186 , ((def_is_ddr4) && (def_cri_dqs_ohm80_p0)) ; # 240/2, 480/2 + 48:59 , 0x180 , ((def_is_ddr4) && (def_cri_dqs_ohm120_p0)) ; # 240/2, 480/0 +# 48:59 , 0x--- , ((def_is_ddr4) && (def_cri_dqs_ohm160_p0)) ; # 240/?, 480/? + 48:59 , 0x100 , ((def_is_ddr4) && (def_cri_dqs_ohm240_p0)) ; # 240/1, 480/0 +# 48:59 , 0x002 , ((def_is_ddr4) && (def_cri_dqs_ohm480_p0)) ; # 240/0, 480/1 + 48:59 , 0x000 , any ; # 240/0, 480/0 +# 60:63 , 0b0000 , any ; # reserved +} + +# DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0 0x07A 0x8001007a0301143f +#scom 0x8001(00,04,08,0C,10)7A0301143f { # NFET_TERM_P1_[0:4] broadcast +scom 0x80013C7A0301143f { # NFET_TERM_P1_[0:4] broadcast + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + # for DDR3 = 1 ohms # ohm/slices + 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p1)) ; # 240/8, 480/0 + 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p1)) ; # 240/6, 480/0 + 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p1)) ; # 240/4, 480/0 +# 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p1)) ; # 240/3, 480/1 + 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p1)) ; # 240/2, 480/2 + 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p1)) ; # 240/2, 480/1 + 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p1)) ; # 240/2, 480/0 + 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p1)) ; # 240/1, 480/1 + 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p1)) ; # 240/1, 480/0 + 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p1)) ; # 240/0, 480/3 + 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p1)) ; # 240/0, 480/2 + 48:59 , 0x000 , any ; # 240/0, 480/0 +# 60:63 , 0b0000 , any ; # reserved +} +# DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0 0x07B 0x8000007B0301143f +#scom 0x8000(00,04,08,0C,10)7B0301143f { # PFET_TERM_P1_[0:4] +scom 0x80013C7B0301143f { # PFET_TERM_P1_[0:4] broadcast bits , scom_data, expr ; +# 0:47 , 0x000000000000, any ; # reserved # for DDR3 = 1 ohms # ohm/slices - 48:59 , 0x03F , ((def_is_ddr3) && (def_cri_dqs_ohm30)) ; # 240/2, 480/4 - 48:59 , 0x01F , ((def_is_ddr3) && (def_cri_dqs_ohm40)) ; # 240/1, 480/4 - 48:59 , 0x00F , ((def_is_ddr3) && (def_cri_dqs_ohm60)) ; # 240/0, 480/4 - 48:59 , 0x007 , ((def_is_ddr3) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm120)) ; # 240/0, 480/2 + 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p1)) ; # 240/8, 480/0 + 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p1)) ; # 240/6, 480/0 + 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p1)) ; # 240/4, 480/0 +# 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p1)) ; # 240/3, 480/1 + 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p1)) ; # 240/2, 480/2 + 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p1)) ; # 240/2, 480/1 + 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p1)) ; # 240/2, 480/0 + 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p1)) ; # 240/1, 480/1 + 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p1)) ; # 240/1, 480/0 + 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p1)) ; # 240/0, 480/3 + 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p1)) ; # 240/0, 480/2 # for DDR4 = 2 - 48:59 , 0x03F , ((def_is_ddr4) && (def_cri_dqs_ohm60)) ; # 240/2, 480/4 - 48:59 , 0x01F , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80)) ; # 240/1, 480/4 -# 48:59 , 0x01F , ((def_is_ddr4) && (def_cri_dqs_ohm80)) ; # 240/1, 480/4 - 48:59 , 0x00F , ((def_is_ddr4) && (def_cri_dqs_ohm120)) ; # 240/0, 480/4 - 48:59 , 0x007 , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 160)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 240)) ; # 240/0, 480/2 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# Joe Iadanza's spreadsheet (from Saravana note 3/28/12 11:20A) has this... -# 48:59 , 0x3C0 , ((def_is_ddr4) && (def_cri_dqs_ohm60)) ; # 240/4, 480/0 -# 48:59 , 0x186 , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80)) ; # 240/2, 480/2 -# 48:59 , 0x180 , ((def_is_ddr4) && (def_cri_dqs_ohm120)) ; # 240/2, 480/0 -# 48:59 , 0x--- , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 160)) ; # 240/?, 480/? -# 48:59 , 0x100 , ((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 240)) ; # 240/1, 480/0 -# 48:59 , 0x000 , any ; # 240/0, 480/0 +# 48:59 , 0x7E6 , ((def_is_ddr4) && (def_cri_dqs_ohm34_p1)) ; # 240/8, 480/2 + 48:59 , 0x7E0 , ((def_is_ddr4) && (def_cri_dqs_ohm40_p1)) ; # 240/8, 480/0 + 48:59 , 0x3C6 , ((def_is_ddr4) && (def_cri_dqs_ohm48_p1)) ; # 240/4, 480/2 + 48:59 , 0x3C0 , ((def_is_ddr4) && (def_cri_dqs_ohm60_p1)) ; # 240/4, 480/0 + 48:59 , 0x186 , ((def_is_ddr4) && (def_cri_dqs_ohm80_p1)) ; # 240/2, 480/2 + 48:59 , 0x180 , ((def_is_ddr4) && (def_cri_dqs_ohm120_p1)) ; # 240/2, 480/0 +# 48:59 , 0x--- , ((def_is_ddr4) && (def_cri_dqs_ohm160_p1)) ; # 240/?, 480/? + 48:59 , 0x100 , ((def_is_ddr4) && (def_cri_dqs_ohm240_p1)) ; # 240/1, 480/0 +# 48:59 , 0x002 , ((def_is_ddr4) && (def_cri_dqs_ohm480_p1)) ; # 240/0, 480/1 + 48:59 , 0x000 , any ; # 240/0, 480/0 +# 60:63 , 0b0000 , any ; # reserved } - # --------------------------------------------------------------------------------------- # Output(DQ/DQS) driver impedance settings # @@ -613,26 +808,33 @@ scom 0x800(0,1)3C7B0301143f { # PFET_TERM_P[0:1]_[0:4] broadcast # # [01:23] [N:P] [0:1][0:4] # DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0 0x078 0x800000780301143f +# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0 0x079 0x800000790301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_NFET_SLICE_L2(0:11) -#scom 0x800(0,1)3C780301143f { # NFET_SLICE_P[0:1]_[0:4] broadcast -scom 0x800(0,1)3C7(8,9)0301143F { # [N:P]FET_SLICE_P[0:1]_[0:4] broadcast - bits , scom_data , expr ; # ohm/slices - 48:59 , 0xFFF , (def_cdi_dqs_ohm24) ; # 240/8, 480/4 - 48:59 , 0x3FF , (def_cdi_dqs_ohm30) ; # 240/6, 480/4 - 48:59 , 0x1FF , (def_cdi_dqs_ohm34) ; # 240/5, 480/4 - 48:59 , 0x0FF , (def_cdi_dqs_ohm40) ; # 240/4, 480/4 - 48:59 , 0x000 , any ; # 240/0, 480/0 +# (00,04,08,0C,10) +#scom 0x80003C780301143f { # NFET_SLICE_P0_[0:4] broadcast +scom 0x80003C7(8,9)0301143F { # [N:P]FET_SLICE_P0_[0:4] broadcast + bits , scom_data , expr ; # ohm/slices +# 0:47 , 0x000000000000, any ; # reserved + 48:59 , 0xFFF , (def_cdi_dqs_ohm24_p0) ; # 240/8, 480/4 + 48:59 , 0x7EF , (def_cdi_dqs_ohm30_p0) ; # 240/6, 480/4 + 48:59 , 0x3EF , (def_cdi_dqs_ohm34_p0) ; # 240/5, 480/4 + 48:59 , 0x3CF , (def_cdi_dqs_ohm40_p0) ; # 240/4, 480/4 + 48:59 , 0x000 , any ; # 240/0, 480/0 +# 60:63 , 0b0000 , any ; # reserved +} + +# DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0 0x078 0x800100780301143f +# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0 0x079 0x800100790301143f +scom 0x80013C7(8,9)0301143F { # [N:P]FET_SLICE_P1_[0:4] broadcast + bits , scom_data , expr ; # ohm/slices +# 0:47 , 0x000000000000, any ; # reserved + 48:59 , 0xFFF , (def_cdi_dqs_ohm24_p1) ; # 240/8, 480/4 + 48:59 , 0x7EF , (def_cdi_dqs_ohm30_p1) ; # 240/6, 480/4 + 48:59 , 0x3EF , (def_cdi_dqs_ohm34_p1) ; # 240/5, 480/4 + 48:59 , 0x3CF , (def_cdi_dqs_ohm40_p1) ; # 240/4, 480/4 + 48:59 , 0x000 , any ; # 240/0, 480/0 +# 60:63 , 0b0000 , any ; # reserved } -# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0 0x079 0x800000790301143f -#scom 0x800(0,1)3C790301143f { # PFET_SLICE_P[0:1]_[0:4] broadcast -# bits , scom_data, expr; -# 48:55 , 0xFF , (def_cdi_dqs_ohm24) ; # 240/8 -# 48:55 , 0x3F , (def_cdi_dqs_ohm30) ; # 240/6 -# 48:55 , 0x1F , (def_cdi_dqs_ohm34) ; # 240/5 -# 48:55 , 0x0F , (def_cdi_dqs_ohm40) ; # 240/4 -# 48:55 , 0x00 , any ; # 240/0 -# 56:59 , 0x0F , any ; # FFE=480/4 -#} #********************************************************************************** #!! DO NOT NEED to set for Centaur from Joe Iadanza. @@ -654,22 +856,24 @@ scom 0x800(0,1)3C7(8,9)0301143F { # [N:P]FET_SLICE_P[0:1]_[0:4] broadcast #! --------------------------------------------------------------------------------------- #! --- PHY01 ADR IO NFET SLICE EN[0:3] P[0:1] ADR[0:3] --------------------------- #! --------------------------------------------------------------------------------------- -#!DPHY01.DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR0 from (alias spydef) +#!DPHY01.DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR0 #!scom 0x800(0,1)(40,44,48,4C)100301143F { #!scom 0x800(0,1)(40,44,48,4C)(10,11,12,13)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] #!scom 0x800(0,1)7C(10,11,12,13)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] via broadcast #! bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved #! 48:63 , 0b1111111111110000 ; #!} #! #! --------------------------------------------------------------------------------------- #! --- PHY01 ADR IO PFET SLICE EN[0:3] P[0:1] ADR[0:3] --------------------------- #! --------------------------------------------------------------------------------------- -#!DPHY01.DDRPHY_ADR_IO_PFET_SLICE_EN0_P0_ADR0 from (alias spydef) +#!DPHY01.DDRPHY_ADR_IO_PFET_SLICE_EN0_P0_ADR0 #!scom 0x800(0,1)(40,44,48,4C)140301143F { #!scom 0x800(0,1)(40,44,48,4C)(14,15,16,17)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] #!scom 0x800(0,1)7C(14,15,16,17)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] via broadcast #! bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved #! 48:63 , 0b1111111111110000 ; #!} #********************************************************************************** @@ -692,53 +896,80 @@ scom 0x800(0,1)3C7(8,9)0301143F { # [N:P]FET_SLICE_P[0:1]_[0:4] broadcast # 11b = 40 ohm # # --------------------------------------------------------------------------------- -# ----------------- Port 0 ADR 0 ----------------------------------------------- +# ----------------- Port 0 ADR 0 -------------------------- !! board wiring dependent !! # --------------------------------------------------------------------------------- # [01:23] [0:1][0:1][0:3] # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0 0x020 0x800040200301143f # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.REG_A_20_L2(0:15) scom 0x800040200301143f { - bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL0 - 48:49 , 0b11 , any ; # SEL0, 40 or anything - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL2 - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL2 - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL2 - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL2 - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL3 - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL3 - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL3 - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL3 -# 48:55 , 0b00000000 , (def_cdi_ctl_ohm15) ; # SEL0:SEL3 -# 48:55 , 0b01010101 , (def_cdi_ctl_ohm20) ; # SEL0:SEL3 -# 48:55 , 0b10101010 , (def_cdi_ctl_ohm30) ; # SEL0:SEL3 -# 48:55 , 0b11111111 , (def_cdi_ctl_ohm40) ; # SEL0:SEL3 -# 48:55 , 0x00 , (def_cdi_ctl_ohm15) ; # SEL0:SEL3 -# 48:55 , 0x55 , (def_cdi_ctl_ohm20) ; # SEL0:SEL3 -# 48:55 , 0xAA , (def_cdi_ctl_ohm30) ; # SEL0:SEL3 -# 48:55 , 0xFF , (def_cdi_ctl_ohm40) ; # SEL0:SEL3 - 56:57 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL7 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 0 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 0, A1_CKE1 + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 1, A0_CS3n + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 2, A1_CKE0 + 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 3, A0_ODT0 + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 4, A_A15 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 5, A_PAR + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 6, A0_CKE1 + 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 7, A0_CS1n + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 0 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 0, C0_CS0n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 1, C_A3 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 2, C1_CS3n + 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 3, C_RASn + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 4, C_A12 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 5, C_A7 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 6, C0_CLK1_p + 60:61 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 60:61 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 60:61 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 62:63 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 7, C0_CLK1_n + 62:63 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; # 48:63 , 0x0000 , any ; # SEL0-7 } # ADR I/O FET Slice Enable Map 1, register 1 containing lanes 8:15 @@ -746,209 +977,410 @@ scom 0x800040200301143f { # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0 scom 0x800040210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL10 clk - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL10 clk - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL10 clk - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL10 clk - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL11 clk - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL11 clk - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL11 clk - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL11 clk +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 0 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 8, A0_CKE0 + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 9, A1_ODT0 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 10, A0_CLK0_p + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 11, A0_CLK0_n + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 0 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 8, C1_CLK1_p + 48:49 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 9, C1_CLK1_n + 50:51 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 10, C1_CKE2 + 52:53 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); + 52:53 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); + 52:53 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); + 54:55 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 11, C0_CKE2 + 54:55 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); + 54:55 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); + 54:55 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); +# 56:63 , 0x00 , any ; # reserved } # ----------------- Port 0 ADR 1 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1 scom 0x800044200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL0 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL0 - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL2 - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL2 - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL2 - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL2 - 54:55 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL3 - 54:55 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL3 - 54:55 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL3 - 54:55 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL3 - 56:57 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 1 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 0, A0_CS0n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 1, A1_CKE3 + 50:51 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); + 50:51 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); + 50:51 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); + 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 2, A1_ODT1 + 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 3, A_A2 + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 4, A_A6 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 5, A_A1 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 6, A_A14 + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 7, A0_CKE2 + 62:63 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); + 62:63 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); + 62:63 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); +# ------ PORT 2 ADR 1 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 0, C_BA2 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 1, C1_CKE1 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 2, C0_ODT1 + 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 3, C_WEn + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 4, C0_CS1n + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 5, C_A11 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 6, C0_CKE3 + 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); + 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); + 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 7, C0_CS2n + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1 scom 0x800044210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL10 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL10 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL10 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL10 - 54:55 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL11 - 54:55 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL11 - 54:55 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL11 - 54:55 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL11 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 1 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 8, A1_CS2n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 9, A1_CKE2 + 50:51 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); + 50:51 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); + 50:51 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 10, A_A4 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 11, A_RASn + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 1 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 8, C0_ODT0 + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 9, C_A8 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 10, C_A5 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 11, C1_CS0n + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; +# 56:63 , 0x00 , any ; # reserved } # ----------------- Port 0 ADR 2 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2 scom 0x800048200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL0 - 48:49 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL0 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL2 - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL2 - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL2 - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL2 - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL3 - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL3 - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL3 - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL3 - 56:57 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL4 clk - 56:57 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL4 clk - 56:57 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL4 clk - 56:57 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL4 clk - 58:59 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL5 clk - 58:59 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL5 clk - 58:59 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL5 clk - 58:59 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL5 clk - 60:61 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 2 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 0, A_A12 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 1, A_A0 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 2, A0_CKE3 + 52:53 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); + 52:53 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); + 52:53 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 3, A1_CS3n + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 4, A1_CLK0_p + 56:57 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 5, A1_CLK0_n + 58:59 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 6, A0_ODT1 + 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 7, A1_CS0n + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 2 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 0, C_A1 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 1, C_A6 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 2, C_A13 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 3, C0_CKE0 + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 4, C1_ODT0 + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 5, C1_CS1n + 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 6, C0_CKE1 + 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 7, C1_CKE0 + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2 scom 0x800048210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL10 clk - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL10 clk - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL10 clk - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL10 clk - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL11 clk - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL11 clk - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL11 clk - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL11 clk - 56:57 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL12 clk - 56:57 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL12 clk - 56:57 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL12 clk - 56:57 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL12 clk - 58:59 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL13 clk - 58:59 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL13 clk - 58:59 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL13 clk - 58:59 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL13 clk +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 2 lanes 8:13 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 8, A1_CS1n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 9, A_A10 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 10, A0_CLK1_n + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 11, A0_CLK1_p + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 12, A1_CLK1_n + 56:57 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 13, A1_CLK1_p + 58:59 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 2 lanes 8:13 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 8, C_A0 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 9, C_BA1 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 10, C0_CLK0_n + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 11, C0_CLK0_p + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 12, C1_CS2n + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 13, C_A10 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; +# 60:63 , 0b0000 , any ; # reserved } # ----------------- Port 0 ADR 3 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3 scom 0x80004c200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL0 - 48:49 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL0 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL2 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL2 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL2 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL2 - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL3 - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL3 - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL3 - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL3 - 56:57 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 3 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 0, A_A13 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 1, A_BA0 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 2, A_WEn + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 3, A0_CS2n + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 4, A_BA1 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 5, A_CASn + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 6, A_A5 + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 7, A_A3 + 62:63 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 3 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 0, C_PAR + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 1, C1_ODT1 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 2, C1_CLK0_p + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 3, C1_CLK0_n + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 4, C_A14 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 5, C_A9 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 6, C_ACTn + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 62:63 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 7, C_A2 + 62:63 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3 scom 0x80004c210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL10 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL10 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL10 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL10 - 54:55 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL11 - 54:55 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL11 - 54:55 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL11 - 54:55 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL11 - 56:57 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL12 - 56:57 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL12 - 56:57 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL12 - 56:57 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL12 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL13 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL13 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL13 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL13 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 3 lanes 8:13 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 8, A_BA2 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 9, A_A11 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 10, A_A7 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 11, A_ACTn + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 12, A_A9 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 13, A_A8 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; +# ------ PORT 2 ADR 3 lanes 8:13 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 8, C1_CKE3 + 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); + 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); + 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 9, C_A15 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 10, C_BA0 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 11, C_CASn + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 12, C_A4 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 13, C0_CS3n + 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; +# 60:63 , 0b0000 , any ; # reserved } # ================================================================================= # ----------------- Port 1 ADR 0 ----------------------------------------------- @@ -956,328 +1388,510 @@ scom 0x80004c210301143f { # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0 scom 0x800140200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL0 clk - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL0 clk - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL0 clk - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL0 clk - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL1 clk - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL1 clk - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL1 clk - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL1 clk - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL2 clk - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL2 clk - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL2 clk - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL2 clk - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL3 clk - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL3 clk - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL3 clk - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL3 clk - 56:57 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 0 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 0, B1_CLK0_n + 48:49 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 1, B1_CLK0_p + 50:51 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 2, B1_CLK1_n + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 3, B1_CLK1_p + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 4, B0_CKE3 + 56:57 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); + 56:57 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); + 56:57 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); + 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 5, B0_CS3n + 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 6, B_BA0 + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 7, B1_ODT1 + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 0 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 0, D1_CKE1 + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 1, D_BA2 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 2, D_A1 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 3, D_A5 + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 4, D_A12 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 5, D_BA0 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 6, D1_CKE2 + 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); + 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); + 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 7, D1_CS1n + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0 scom 0x800140210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL10 - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL10 - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL10 - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL10 - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL11 - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL11 - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL11 - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL11 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 0 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 8, B1_CKE3 + 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); + 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); + 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 9, B_A15 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 10, B1_CS2n + 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 11, B0_CKE1 + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 0 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 8, D0_CKE0 + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 9, D0_CS2n + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 10, D1_CLK0_p + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 11, D1_CLK0_n + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; +# 56:63 , 0x00 , any ; # reserved } # ----------------- Port 1 ADR 1 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1 scom 0x800144200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL0 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL0 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL2 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL2 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL2 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL2 - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL3 - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL3 - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL3 - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL3 - 56:57 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 1 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 0, B0_CKE2 + 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); + 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); + 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 1, B_A7 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 2, B_A10 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 3, B1_CKE1 + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 4, B0_CS1n + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 5, B_A8 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 6, B_A6 + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 7, B1_CS3n + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 1 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 0, D_A8 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 1, D_A13 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 2, D0_ODT1 + 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 3, D_PAR + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 4, D1_CS0n + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 5, D_A11 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 6, D0_CKE1 + 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 62:63 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 7, D_WEn + 62:63 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1 scom 0x800144210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL10 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL10 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL10 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL10 - 54:55 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL11 - 54:55 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL11 - 54:55 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL11 - 54:55 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL11 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 1 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 8, B_A4 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 9, B1_CS1n + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 10, B_A1 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 11, B_BA1 + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 1 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 8, D0_CKE3 + 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); + 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); + 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 9, D1_ODT0 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 10, D_RASn + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 11, D0_CS1n + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; +# 56:63 , 0x00 , any ; # reserved } # ----------------- Port 1 ADR 2 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2 scom 0x800148200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL0 - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL0 - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL2 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL2 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL2 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL2 - 54:55 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL3 - 54:55 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL3 - 54:55 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL3 - 54:55 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL3 - 56:57 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 2 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 0, B0_CS2n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 1, B0_ODT0 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 2, B_WEn + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 3, B_A2 + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 4, B0_ODT1 + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 5, B0_CS0n + 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 6, B_A3 + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 62:63 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 7, B_A0 + 62:63 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 2 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 0, D0_CS0n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 1, D_A10 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 2, D_A4 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 3, D1_CS3n + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 4, D_ACTn + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 5, D_A9 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 6, D1_CKE3 + 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); + 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); + 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 7, D1_CKE0 + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2 scom 0x800148210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL8 clk - 48:49 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL8 clk - 48:49 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL8 clk - 48:49 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL8 clk - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL9 clk - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL9 clk - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL9 clk - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL9 clk - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL10 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL10 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL10 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL10 - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL11 - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL11 - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL11 - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL11 - 56:57 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL12 - 56:57 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL12 - 56:57 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL12 - 56:57 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL12 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL13 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL13 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL13 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL13 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 2 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 8, B0_CLK1_p + 48:49 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 9, B0_CLK1_n + 50:51 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 10, B_CASn + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 11, B1_CS0n + 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 12, B1_CKE0 + 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 13, B_A12 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 2 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 8, D0_CS3n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 9, D_A2 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 10, D1_CLK1_n + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 11, D1_CLK1_p + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 12, D0_CLK1_n + 56:57 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 13, D0_CLK1_p + 58:59 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; +# 60:63 , 0b0000 , any ; # reserved } # ----------------- Port 1 ADR 3 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3 scom 0x80014c200301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL0 - 48:49 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL0 - 48:49 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL0 - 48:49 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL0 - 50:51 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL1 - 50:51 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL1 - 50:51 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL1 - 50:51 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL1 - 52:53 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL2 clk - 52:53 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL2 clk - 52:53 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL2 clk - 52:53 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL2 clk - 54:55 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL3 clk - 54:55 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL3 clk - 54:55 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL3 clk - 54:55 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL3 clk - 56:57 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL4 - 56:57 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL4 - 56:57 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL4 - 56:57 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL4 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL5 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL5 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL5 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL5 - 60:61 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL6 - 60:61 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL6 - 60:61 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL6 - 60:61 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL6 - 62:63 , 0b00 , (def_cdi_ctl_ohm15) ; # SEL7 - 62:63 , 0b01 , (def_cdi_ctl_ohm20) ; # SEL7 - 62:63 , 0b10 , (def_cdi_ctl_ohm30) ; # SEL7 - 62:63 , 0b11 , (def_cdi_ctl_ohm40) ; # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 3 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 0, B_A11 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 1, B0_CKE0 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 2, B0_CLK0_n + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 3, B0_CLK0_p + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 4, B_A13 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 5, B_A14 + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 6, B1_CKE2 + 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); + 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); + 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); + 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 7, B1_ODT0 + 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; + 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; + 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 3 lanes 0:7 --------------------------------------------- + 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 0, D1_CS2n + 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 1, D0_ODT0 + 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 2, D0_CLK0_n + 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 3, D0_CLK0_p + 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 4, D_A6 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 5, D1_ODT1 + 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; + 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; + 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; + 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 6, D_A0 + 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 62:63 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 7, D_CASn + 62:63 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 62:63 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 62:63 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; } # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3 scom 0x80014c210301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL8 - 48:49 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL8 - 48:49 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL8 - 48:49 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL8 - 50:51 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL9 - 50:51 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL9 - 50:51 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL9 - 50:51 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL9 - 52:53 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL10 - 52:53 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL10 - 52:53 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL10 - 52:53 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL10 - 54:55 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL11 - 54:55 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL11 - 54:55 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL11 - 54:55 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL11 - 56:57 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL12 - 56:57 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL12 - 56:57 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL12 - 56:57 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL12 - 58:59 , 0b00 , (def_cdi_cmd_ohm15) ; # SEL13 - 58:59 , 0b01 , (def_cdi_cmd_ohm20) ; # SEL13 - 58:59 , 0b10 , (def_cdi_cmd_ohm30) ; # SEL13 - 58:59 , 0b11 , (def_cdi_cmd_ohm40) ; # SEL13 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 3 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 8, B_A9 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 9, B_BA2 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 10, B_RASn + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 11, B_ACTn + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 12, B_A5 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; + 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 13, B_PAR + 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; + 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; + 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; +# ------ PORT 3 ADR 3 lanes 8:11 -------------------------------------------- + 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 8, D_A14 + 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 9, D_A3 + 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 10, D_A7 + 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 11, D_A15 + 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 12, D_BA1 + 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; + 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; + 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; + 58:59 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 13, D0_CKE2 + 58:59 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); + 58:59 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); + 58:59 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); +# 60:63 , 0b0000 , any ; # reserved } #********************************************************************************** # ADR Slew Calibration control default=0 -# -# Controls the circuit that performs the ADR slew calibration. -# -# [01:23] [0:1] [0:1] # DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0 0x039 0x800080390301143f -# Controls the circuit that performs the ADR slew calibration. # -scom 0x800080390301143f { - bits , scom_data ; - 48 , 0b0 ; # enable - 49 , 0b1 ; # start -# 50 , 0b0 ; # reserved - 51 , 0b1 ; # override enable - 52:55 , 0b0100 ; # override vector -# 56:58 , 0b010 ; # reserved - 59:63 , 0b10111 ; # slew target phase rotator offset -} -# -# !! looks like 4,5,6V/ns for 1.35V and 4,5V/ns at 1.2V, need to add this to the -# ddr_reset_phy procedure. Waiting on details from analog PHY team for settings. -# -#********************************************************************************** - -# --------------------------------------------------------------------------------------- -# Configure slew rate mux(CTL) registers(4) -# CTL0 = CMD, CTL1 = CNTL, CTL2 = unused, CTL3 = unused -# -# ATTR_EFF_CEN_SLEW_RATE_CMD 0=slow, 15=fast use in CTL0 -# ATTR_EFF_CEN_SLEW_RATE_CNTL 0=slow, 15=fast use in CTL1 -# -# choices... 0=3.61, 1=4.33, 2=5.41, 3=6.69, 4=8.11, 5=8.58 V/ns -# 6..F is approximately 180mV/step, F=10.56 V/ns +# --------------------------------------------------------------------------------- +# Configure slew rate mux(CTL) registers(4) slew mapping/slew mux +# set in ddrphy_reset procedure via FN call +# CTL0 = CMD, CTL1 = CNTL, CTL2 = CLK, CTL3 = SPCKE # -# [01:23] [0:1][0:3] +# [01:23] [0:1][0:3] # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0 0x01A 0x8000401a0301143f #scom 0x8000(40,44,48,4c)1A0301143f { # VALUE_P0_ADR[0:3] -scom 0x800(0,1)7C1A0301143f { # VALUE_P[0:1]_ADR[0:3] broadcast - bits , scom_data , expr ; - # SLEW_CTL0, used for command - 48:51 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 0) ; # slow - 48:51 , 0b0001 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 1) ; # faster . - 48:51 , 0b0010 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 2) ; # faster .. - 48:51 , 0b0011 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 3) ; # faster ... - 48:51 , 0b0100 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 4) ; # faster .... - 48:51 , 0b0101 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 5) ; # faster ..... - 48:51 , 0b0110 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 6) ; # faster ...... - 48:51 , 0b0111 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 7) ; # faster ....... - 48:51 , 0b1000 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 8) ; # faster ........ - 48:51 , 0b1001 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 9) ; # faster ......... - 48:51 , 0b1010 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 10) ; # faster .......... - 48:51 , 0b1011 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 11) ; # faster ........... - 48:51 , 0b1100 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 12) ; # faster ............ - 48:51 , 0b1101 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 13) ; # faster ............. - 48:51 , 0b1110 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 14) ; # faster .............. - 48:51 , 0b1111 , (ATTR_EFF_CEN_SLEW_RATE_CMD == 15) ; # fastest............... - # SLEW_CTL1, used for control - 52:55 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 0) ; # slow - 52:55 , 0b0001 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 1) ; # faster . - 52:55 , 0b0010 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 2) ; # faster .. - 52:55 , 0b0011 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 3) ; # faster ... - 52:55 , 0b0100 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 4) ; # faster .... - 52:55 , 0b0101 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 5) ; # faster ..... - 52:55 , 0b0110 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 6) ; # faster ...... - 52:55 , 0b0111 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 7) ; # faster ....... - 52:55 , 0b1000 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 8) ; # faster ........ - 52:55 , 0b1001 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 9) ; # faster ......... - 52:55 , 0b1010 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 10) ; # faster .......... - 52:55 , 0b1011 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 11) ; # faster ........... - 52:55 , 0b1100 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 12) ; # faster ............ - 52:55 , 0b1101 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 13) ; # faster ............. - 52:55 , 0b1110 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 14) ; # faster .............. - 52:55 , 0b1111 , (ATTR_EFF_CEN_SLEW_RATE_CNTL == 15) ; # fastest............... - # SLEW_CTL2 3.61 V/ns, not used currently - 56:59 , 0b0000 , any ; # slow - # SLEW_CTL3 3.61 V/ns, not used currently - 60:63 , 0b0000 , any ; # slow -} +#scom 0x800(0,1)7C1A0301143f { # VALUE_P[0:1]_ADR[0:3] broadcast +# bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + # SLEW_CTL0, used for command (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) +# 48:51 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_ADDR[0]) ; + # SLEW_CTL1, used for control (CKE0:1, CKE4:5, ODT, CSN0:7) +# 52:55 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_CNTL[0]) ; + # SLEW_CTL2, used for clocks (CLK0:3) +# 56:59 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_CLK[0]) ; + # SLEW_CTL3, used for spare drams (CKE2:3, CKE6:7) +# 60:63 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_SPCKE[0) ; +#} +#********************************************************************************** -# --------------------------------------------------------------------------------------- +# --------------------------------------------------------------------------------- # Set slew rate to select CMD(CTL0) or CNTL(CTL1) # # MAP0 = SLEW_CTL_SEL{0:7} MAP1 = SLEW_CTL_SEL{8:15} @@ -1288,23 +1902,30 @@ scom 0x800(0,1)7C1A0301143f { # VALUE_P[0:1]_ADR[0:3] broadcast # ----------------- Port 0 ADR 0 ----------------------------------------------- scom 0x8000402a0301143f { # MAP0_P0_ADR0 bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL0 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL1 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL2 - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL3 - 56:57 , 0b00 , (def_is_mba01) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba01) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba01) ; # CNTL # SEL7 - # ----------------- Port 2 ADR 0 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL0 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL1 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL2 - 54:55 , 0b00 , (def_is_mba23) ; # CMD # SEL3 - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba23) ; # CNTL # SEL6 clk - 62:63 , 0b01 , (def_is_mba23) ; # CNTL # SEL7 clk +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 0 lanes 0:7 --------------------------------------------- +# A1_CKE1, A0_CS3n, A1_CKE0, A0_ODT0, A_A15, A_PAR, A0_CKE1, A0_CS1n +# 48:63 , 0x5505 , (def_is_mba01) ; +# ------ PORT 2 ADR 0 lanes 0:7 --------------------------------------------- +# C0_CS0n, C_A3, C1_CS3n, C_RASn, C_A12, C_A7, C0_CLK1_p, C0_CLK1_n +# 48:63 , 0x440A , (def_is_mba23) ; + 48:49 , 0b01 , (def_is_mba01) ; # 0 CNTL , A1_CKE1 + 50:51 , 0b01 , (def_is_mba01) ; # 1 CNTL , A0_CS3n + 52:53 , 0b01 , (def_is_mba01) ; # 2 CNTL , A1_CKE0 + 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , A0_ODT0 + 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , A_A15 + 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , A_PAR + 60:61 , 0b01 , (def_is_mba01) ; # 6 CNTL , A0_CKE1 + 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , A0_CS1n + # ----------------- Port 2 ADR 0 Map 0 ---------------------- + 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , C0_CS0n + 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , C_A3 + 52:53 , 0b01 , (def_is_mba23) ; # 2 CNTL , C1_CS3n + 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , C_RASn + 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , C_A12 + 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , C_A7 + 60:61 , 0b10 , (def_is_mba23) ; # 6 CLK , C0_CLK1_p + 62:63 , 0b10 , (def_is_mba23) ; # 7 CLK , C0_CLK1_n } # ADR I/O FET Slice Enable Map 1 # Register 1 containing lanes 8:15 @@ -1312,128 +1933,181 @@ scom 0x8000402a0301143f { # MAP0_P0_ADR0 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0 0x02b 0x8000402b0301143f scom 0x8000402b0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL8 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL9 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL10 clk - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL11 clk +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 0 lanes 8:11 -------------------------------------------- +# A0_CKE0, A1_ODT0, A0_CLK0_p, A0_CLK0_n +# 48:55 , 0x5A , (def_is_mba01) ; +# ------ PORT 2 ADR 0 lanes 8:11 -------------------------------------------- +# C1_CLK1_p, C1_CLK1_n, C1_CKE2, C0_CKE2 +# 48:55 , 0xAF , (def_is_mba23) ; + 48:49 , 0b01 , (def_is_mba01) ; # 8 CNTL , A0_CKE0 + 50:51 , 0b01 , (def_is_mba01) ; # 9 CNTL , A1_ODT0 + 52:53 , 0b10 , (def_is_mba01) ; #10 CLK , A0_CLK0_p + 54:55 , 0b10 , (def_is_mba01) ; #11 CLK , A0_CLK0_n # ----------------- Port 2 ADR 0 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL8 clk - 50:51 , 0b01 , (def_is_mba23) ; # CNTL # SEL9 clk - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL10 - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL11 + 48:49 , 0b10 , (def_is_mba23) ; # 8 CLK , C1_CLK1_p + 50:51 , 0b10 , (def_is_mba23) ; # 9 CLK , C1_CLK1_n + 52:53 , 0b11 , (def_is_mba23) ; #10 SPCKE , C1_CKE2 + 54:55 , 0b11 , (def_is_mba23) ; #11 SPCKE , C0_CKE2 +# 56:63 , 0b00000000 , any ; # reserved } # ----------------- Port 0 ADR 1 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1 scom 0x8000442a0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL0 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL1 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL2 - 54:55 , 0b00 , (def_is_mba01) ; # CMD # SEL3 - 56:57 , 0b00 , (def_is_mba01) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL5 - 60:61 , 0b00 , (def_is_mba01) ; # CMD # SEL6 - 62:63 , 0b01 , (def_is_mba01) ; # CNTL # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 1 lanes 0:7 --------------------------------------------- +# A0_CS0n, A1_CKE3, A1_ODT1, A_A2, A_A6, A_A1, A_A14, A0_CKE2 +# 48:63 , 0x7403 , (def_is_mba01) ; +# ------ PORT 2 ADR 1 lanes 0:7 --------------------------------------------- +# C_BA2, C1_CKE1, C0_ODT1, C_WEn, C0_CS1n, C_A11, C0_CKE3, C0_CS2n +# 48:63 , 0x144D , (def_is_mba23) ; + 48:49 , 0b01 , (def_is_mba01) ; # 0 CNTL , A0_CS0n + 50:51 , 0b11 , (def_is_mba01) ; # 1 SPCKE , A1_CKE3 + 52:53 , 0b01 , (def_is_mba01) ; # 2 CNTL , A1_ODT1 + 54:55 , 0b00 , (def_is_mba01) ; # 3 ADDR , A_A2 + 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , A_A6 + 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , A_A1 + 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , A_A14 + 62:63 , 0b11 , (def_is_mba01) ; # 7 SPCKE , A0_CKE2 # ----------------- Port 2 ADR 1 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # CMD # SEL0 - 50:51 , 0b01 , (def_is_mba23) ; # CNTL # SEL1 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL2 - 54:55 , 0b00 , (def_is_mba23) ; # CMD # SEL3 - 56:57 , 0b01 , (def_is_mba23) ; # CNTL # SEL4 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba23) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba23) ; # CNTL # SEL7 + 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , C_BA2 + 50:51 , 0b01 , (def_is_mba23) ; # 1 CNTL , C1_CKE1 + 52:53 , 0b01 , (def_is_mba23) ; # 2 CNTL , C0_ODT1 + 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , C_WEn + 56:57 , 0b01 , (def_is_mba23) ; # 4 CNTL , C0_CS1n + 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , C_A11 + 60:61 , 0b11 , (def_is_mba23) ; # 6 SPCKE , C0_CKE3 + 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , C0_CS2n } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1 scom 0x8000442b0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL8 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL9 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL10 - 54:55 , 0b00 , (def_is_mba01) ; # CMD # SEL11 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 1 lanes 8:11 -------------------------------------------- +# A1_CS2n, A1_CKE2, A_A4, A_RASn +# 48:55 , 0x70 , (def_is_mba01) ; +# ------ PORT 2 ADR 1 lanes 8:11 -------------------------------------------- +# C0_ODT0, C_A8, C_A5, C1_CS0n +# 48:55 , 0x41 , (def_is_mba23) ; + 48:49 , 0b01 , (def_is_mba01) ; # 8 CNTL , A1_CS2n + 50:51 , 0b11 , (def_is_mba01) ; # 9 SPCKE , A1_CKE2 + 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , A_A4 + 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , A_RASn # ----------------- Port 2 ADR 1 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL8 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL9 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL10 - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL11 + 48:49 , 0b01 , (def_is_mba23) ; # 8 CNTL , C0_ODT0 + 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , C_A8 + 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , C_A5 + 54:55 , 0b01 , (def_is_mba23) ; #11 CNTL , C1_CS0n +# 56:63 , 0b00000000 , any ; # reserved } # ----------------- Port 0 ADR 2 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2 scom 0x8000482a0301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_is_mba01) ; # CMD # SEL0 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL1 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL2 - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL3 - 56:57 , 0b01 , (def_is_mba01) ; # CNTL # SEL4 clk - 58:59 , 0b01 , (def_is_mba01) ; # CNTL # SEL5 clk - 60:61 , 0b01 , (def_is_mba01) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba01) ; # CNTL # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 2 lanes 0:7 --------------------------------------------- +# A_A12, A_A0, A0_CKE3, A1_CS3n, A1_CLK0_p, A1_CLK0_n, A0_ODT1, A1_CS0n +# 48:63 , 0x0DA5 , (def_is_mba01) ; +# ------ PORT 2 ADR 2 lanes 0:7 --------------------------------------------- +# C_A1, C_A6, C_A13, C0_CKE0, C1_ODT0, C1_CS1n, C0_CKE1, C1_CKE0 +# 48:63 , 0x0155 , (def_is_mba23) ; + 48:49 , 0b00 , (def_is_mba01) ; # 0 ADDR , A_A12 + 50:51 , 0b00 , (def_is_mba01) ; # 1 ADDR , A_A0 + 52:53 , 0b11 , (def_is_mba01) ; # 2 SPCKE , A0_CKE3 + 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , A1_CS3n + 56:57 , 0b10 , (def_is_mba01) ; # 4 CLK , A1_CLK0_p + 58:59 , 0b10 , (def_is_mba01) ; # 5 CLK , A1_CLK0_n + 60:61 , 0b01 , (def_is_mba01) ; # 6 CNTL , A0_ODT1 + 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , A1_CS0n # ----------------- Port 2 ADR 2 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # CMD # SEL0 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL1 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL2 - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL3 - 56:57 , 0b01 , (def_is_mba23) ; # CNTL # SEL4 - 58:59 , 0b01 , (def_is_mba23) ; # CNTL # SEL5 - 60:61 , 0b01 , (def_is_mba23) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba23) ; # CNTL # SEL7 + 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , C_A1 + 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , C_A6 + 52:53 , 0b00 , (def_is_mba23) ; # 2 ADDR , C_A13 + 54:55 , 0b01 , (def_is_mba23) ; # 3 CNTL , C0_CKE0 + 56:57 , 0b01 , (def_is_mba23) ; # 4 CNTL , C1_ODT0 + 58:59 , 0b01 , (def_is_mba23) ; # 5 CNTL , C1_CS1n + 60:61 , 0b01 , (def_is_mba23) ; # 6 CNTL , C0_CKE1 + 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , C1_CKE0 } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2 scom 0x8000482b0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL8 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL9 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL10 clk - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL11 clk - 56:57 , 0b01 , (def_is_mba01) ; # CNTL # SEL12 clk - 58:59 , 0b01 , (def_is_mba01) ; # CNTL # SEL13 clk +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 2 lanes 8:13 -------------------------------------------- +# A1_CS1n, A_A10, A0_CLK1_n, A0_CLK1_p, A1_CLK1_n, A1_CLK1_p +# 48:59 , 0x4AA , (def_is_mba01) ; +# ------ PORT 2 ADR 2 lanes 8:13 -------------------------------------------- +# C_A0, C_BA1, C0_CLK0_n, C0_CLK0_p, C1_CS2n, C_A10 +# 48:59 , 0x0A4 , (def_is_mba23) ; + 48:49 , 0b01 , (def_is_mba01) ; # 8 CNTL , A1_CS1n + 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , A_A10 + 52:53 , 0b10 , (def_is_mba01) ; #10 CLK , A0_CLK1_n + 54:55 , 0b10 , (def_is_mba01) ; #11 CLK , A0_CLK1_p + 56:57 , 0b10 , (def_is_mba01) ; #12 CLK , A1_CLK1_n + 58:59 , 0b10 , (def_is_mba01) ; #13 CLK , A1_CLK1_p # ----------------- Port 2 ADR 2 Map 1 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # CMD # SEL8 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL9 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL10 clk - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL11 clk - 56:57 , 0b01 , (def_is_mba23) ; # CNTL # SEL12 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL13 + 48:49 , 0b00 , (def_is_mba23) ; # 8 ADDR , C_A0 + 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , C_BA1 + 52:53 , 0b10 , (def_is_mba23) ; #10 CLK , C0_CLK0_n + 54:55 , 0b10 , (def_is_mba23) ; #11 CLK , C0_CLK0_p + 56:57 , 0b01 , (def_is_mba23) ; #12 CNTL , C1_CS2n + 58:59 , 0b00 , (def_is_mba23) ; #13 ADDR , C_A10 +# 60:63 , 0b0000 , any ; # reserved } # ----------------- Port 0 ADR 3 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3 scom 0x80004c2a0301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_is_mba01) ; # CMD # SEL0 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL1 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL2 - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL3 - 56:57 , 0b00 , (def_is_mba01) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL5 - 60:61 , 0b00 , (def_is_mba01) ; # CMD # SEL6 - 62:63 , 0b00 , (def_is_mba01) ; # CMD # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 3 lanes 0:7 --------------------------------------------- +# A_A13, A_BA0, A_WEn, A0_CS2n, A_BA1, A_CASn, A_A5, A_A3 +# 48:63 , 0x0100 , (def_is_mba01) ; +# ------ PORT 2 ADR 3 lanes 0:7 --------------------------------------------- +# C_PAR, C1_ODT1, C1_CLK0_p, C1_CLK0_n, C_A14, C_A9, C_ACTn, C_A2 +# 48:63 , 0x1A00 , (def_is_mba23) ; + 48:49 , 0b00 , (def_is_mba01) ; # 0 ADDR , A_A13 + 50:51 , 0b00 , (def_is_mba01) ; # 1 ADDR , A_BA0 + 52:53 , 0b00 , (def_is_mba01) ; # 2 ADDR , A_WEn + 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , A0_CS2n + 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , A_BA1 + 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , A_CASn + 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , A_A5 + 62:63 , 0b00 , (def_is_mba01) ; # 7 ADDR , A_A3 # ----------------- Port 2 ADR 3 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # CMD # SEL0 - 50:51 , 0b01 , (def_is_mba23) ; # CNTL # SEL1 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL2 clk - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL3 clk - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL5 - 60:61 , 0b00 , (def_is_mba23) ; # CMD # SEL6 - 62:63 , 0b00 , (def_is_mba23) ; # CMD # SEL7 + 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , C_PAR + 50:51 , 0b01 , (def_is_mba23) ; # 1 CNTL , C1_ODT1 + 52:53 , 0b10 , (def_is_mba23) ; # 2 CLK , C1_CLK0_p + 54:55 , 0b10 , (def_is_mba23) ; # 3 CLK , C1_CLK0_n + 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , C_A14 + 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , C_A9 + 60:61 , 0b00 , (def_is_mba23) ; # 6 ADDR , C_ACTn + 62:63 , 0b00 , (def_is_mba23) ; # 7 ADDR , C_A2 } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3 scom 0x80004c2b0301143f { - bits , scom_data , expr ; - 48:49 , 0b00 , (def_is_mba01) ; # CMD # SEL8 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL9 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL10 - 54:55 , 0b00 , (def_is_mba01) ; # CMD # SEL11 - 56:57 , 0b00 , (def_is_mba01) ; # CMD # SEL12 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL13 + bits , scom_data , expr ; # signal +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 0 ADR 3 lanes 8:13 -------------------------------------------- +# A_BA2, A_A11, A_A7, A_ACTn, A_A9, A_A8 +# 48:59 , 0x000 , (def_is_mba01) ; +# ------ PORT 2 ADR 3 lanes 8:13 -------------------------------------------- +# C1_CKE3, C_A15, C_BA0, C_CASn, C_A4, C0_CS3n +# 48:59 , 0xC01 , (def_is_mba23) ; + 48:49 , 0b00 , (def_is_mba01) ; # 8 ADDR , A_BA2 + 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , A_A11 + 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , A_A7 + 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , A_ACTn + 56:57 , 0b00 , (def_is_mba01) ; #12 ADDR , A_A9 + 58:59 , 0b00 , (def_is_mba01) ; #13 ADDR , A_A8 # ----------------- Port 2 ADR 3 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL8 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL9 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL10 - 54:55 , 0b00 , (def_is_mba23) ; # CMD # SEL11 - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL12 - 58:59 , 0b01 , (def_is_mba23) ; # CNTL # SEL13 + 48:49 , 0b11 , (def_is_mba23) ; # 8 SPCKE , C1_CKE3 + 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , C_A15 + 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , C_BA0 + 54:55 , 0b00 , (def_is_mba23) ; #11 ADDR , C_CASn + 56:57 , 0b00 , (def_is_mba23) ; #12 ADDR , C_A4 + 58:59 , 0b01 , (def_is_mba23) ; #13 CNTL , C0_CS3n +# 60:63 , 0b0000 , any ; # reserved } # ================================================================================= # ----------------- Port 1 ADR 0 ----------------------------------------------- @@ -1441,179 +2115,220 @@ scom 0x80004c2b0301143f { # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0 scom 0x8001402a0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL0 clk - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL1 clk - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL2 clk - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL3 clk - 56:57 , 0b01 , (def_is_mba01) ; # CNTL # SEL4 - 58:59 , 0b01 , (def_is_mba01) ; # CNTL # SEL5 - 60:61 , 0b00 , (def_is_mba01) ; # CMD # SEL6 - 62:63 , 0b01 , (def_is_mba01) ; # CNTL # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 0 lanes 0:7 --------------------------------------------- +# B1_CLK0_n, B1_CLK0_p, B1_CLK1_n, B1_CLK1_p, B0_CKE3, B0_CS3n, B_BA0, B1_ODT1 +# 48:63 , 0xAAD1 , (def_is_mba01) ; +# ------ PORT 3 ADR 0 lanes 0:7 --------------------------------------------- +# D1_CKE1, D_BA2, D_A1, D_A5, D_A12, D_BA0, D1_CKE2, D1_CS1n +# 48:63 , 0x400D , (def_is_mba23) ; + 48:49 , 0b10 , (def_is_mba01) ; # 0 CLK , B1_CLK0_n + 50:51 , 0b10 , (def_is_mba01) ; # 1 CLK , B1_CLK0_p + 52:53 , 0b10 , (def_is_mba01) ; # 2 CLK , B1_CLK1_n + 54:55 , 0b10 , (def_is_mba01) ; # 3 CLK , B1_CLK1_p + 56:57 , 0b11 , (def_is_mba01) ; # 4 SPCKE , B0_CKE3 + 58:59 , 0b01 , (def_is_mba01) ; # 5 CNTL , B0_CS3n + 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , B_BA0 + 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , B1_ODT1 # ----------------- Port 3 ADR 0 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL0 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL1 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL2 - 54:55 , 0b00 , (def_is_mba23) ; # CMD # SEL3 - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba23) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba23) ; # CNTL # SEL7 + 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , D1_CKE1 + 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , D_BA2 + 52:53 , 0b00 , (def_is_mba23) ; # 2 ADDR , D_A1 + 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , D_A5 + 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , D_A12 + 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , D_BA0 + 60:61 , 0b11 , (def_is_mba23) ; # 6 SPCKE , D1_CKE2 + 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , D1_CS1n } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0 scom 0x8001402b0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL8 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL9 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL10 - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL11 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 0 lanes 8:11 -------------------------------------------- +# B1_CKE3, B_A15, B1_CS2n, B0_CKE1 +# 48:55 , 0xC5 , (def_is_mba01) ; +# ------ PORT 3 ADR 0 lanes 8:11 -------------------------------------------- +# D0_CKE0, D0_CS2n, D1_CLK0_p, D1_CLK0_n +# 48:55 , 0x5A , (def_is_mba23) ; + 48:49 , 0b11 , (def_is_mba01) ; # 8 SPCKE , B1_CKE3 + 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , B_A15 + 52:53 , 0b01 , (def_is_mba01) ; #10 CNTL , B1_CS2n + 54:55 , 0b01 , (def_is_mba01) ; #11 CNTL , B0_CKE1 # ----------------- Port 3 ADR 0 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL8 - 50:51 , 0b01 , (def_is_mba23) ; # CNTL # SEL9 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL10 clk - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL11 clk + 48:49 , 0b01 , (def_is_mba23) ; # 8 CNTL , D0_CKE0 + 50:51 , 0b01 , (def_is_mba23) ; # 9 CNTL , D0_CS2n + 52:53 , 0b10 , (def_is_mba23) ; #10 CLK , D1_CLK0_p + 54:55 , 0b10 , (def_is_mba23) ; #11 CLK , D1_CLK0_n +# 56:63 , 0b00000000 , any ; # reserved } # ----------------- Port 1 ADR 1 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1 scom 0x8001442a0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL0 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL1 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL2 - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL3 - 56:57 , 0b01 , (def_is_mba01) ; # CNTL # SEL4 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL5 - 60:61 , 0b00 , (def_is_mba01) ; # CMD # SEL6 - 62:63 , 0b01 , (def_is_mba01) ; # CNTL # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 1 lanes 0:7 --------------------------------------------- +# B0_CKE2, B_A7, B_A10, B1_CKE1, B0_CS1n, B_A8, B_A6, B1_CS3n +# 48:63 , 0xC141 , (def_is_mba01) ; +# ------ PORT 3 ADR 1 lanes 0:7 --------------------------------------------- +# D_A8, D_A13, D0_ODT1, D_PAR, D1_CS0n, D_A11, D0_CKE1, D_WEn +# 48:63 , 0x0444 , (def_is_mba23) ; + 48:49 , 0b11 , (def_is_mba01) ; # 0 SPCKE , B0_CKE2 + 50:51 , 0b00 , (def_is_mba01) ; # 1 ADDR , B_A7 + 52:53 , 0b00 , (def_is_mba01) ; # 2 ADDR , B_A10 + 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , B1_CKE1 + 56:57 , 0b01 , (def_is_mba01) ; # 4 CNTL , B0_CS1n + 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , B_A8 + 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , B_A6 + 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , B1_CS3n # ----------------- Port 3 ADR 1 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # CMD # SEL0 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL1 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL2 - 54:55 , 0b00 , (def_is_mba23) ; # CMD # SEL3 - 56:57 , 0b01 , (def_is_mba23) ; # CNTL # SEL4 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba23) ; # CNTL # SEL6 - 62:63 , 0b00 , (def_is_mba23) ; # CMD # SEL7 + 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , D_A8 + 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , D_A13 + 52:53 , 0b01 , (def_is_mba23) ; # 2 CNTL , D0_ODT1 + 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , D_PAR + 56:57 , 0b01 , (def_is_mba23) ; # 4 CNTL , D1_CS0n + 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , D_A11 + 60:61 , 0b01 , (def_is_mba23) ; # 6 CNTL , D0_CKE1 + 62:63 , 0b00 , (def_is_mba23) ; # 7 ADDR , D_WEn } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1 scom 0x8001442b0301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_is_mba01) ; # CMD # SEL8 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL9 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL10 - 54:55 , 0b00 , (def_is_mba01) ; # CMD # SEL11 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 1 lanes 8:11 -------------------------------------------- +# B_A4, B1_CS1n, B_A1, B_BA1 +# 48:55 , 0x10 , (def_is_mba01) ; +# ------ PORT 3 ADR 1 lanes 8:11 -------------------------------------------- +# D0_CKE3, D1_ODT0, D_RASn, D0_CS1n +# 48:55 , 0xD1 , (def_is_mba23) ; + 48:49 , 0b00 , (def_is_mba01) ; # 8 ADDR , B_A4 + 50:51 , 0b01 , (def_is_mba01) ; # 9 CNTL , B1_CS1n + 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , B_A1 + 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , B_BA1 # ----------------- Port 3 ADR 1 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL8 - 50:51 , 0b01 , (def_is_mba23) ; # CNTL # SEL9 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL10 - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL11 + 48:49 , 0b11 , (def_is_mba23) ; # 8 CNTL , D0_CKE3 + 50:51 , 0b01 , (def_is_mba23) ; # 9 CNTL , D1_ODT0 + 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , D_RASn + 54:55 , 0b01 , (def_is_mba23) ; #11 CNTL , D0_CS1n +# 56:63 , 0b00000000 , any ; # reserved } # ----------------- Port 1 ADR 2 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2 scom 0x8001482a0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL0 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL1 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL2 - 54:55 , 0b00 , (def_is_mba01) ; # CMD # SEL3 - 56:57 , 0b01 , (def_is_mba01) ; # CNTL # SEL4 - 58:59 , 0b01 , (def_is_mba01) ; # CNTL # SEL5 - 60:61 , 0b00 , (def_is_mba01) ; # CMD # SEL6 - 62:63 , 0b00 , (def_is_mba01) ; # CMD # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 2 lanes 0:7 --------------------------------------------- +# B0_CS2n, B0_ODT0, B_WEn, B_A2, B0_ODT1, B0_CS0n, B_A3, B_A0 +# 48:63 , 0x5050 , (def_is_mba01) ; +# ------ PORT 3 ADR 2 lanes 0:7 --------------------------------------------- +# D0_CS0n, D_A10, D_A4, D1_CS3n, D_ACTn, D_A9, D1_CKE3, D1_CKE0 +# 48:63 , 0x410D , (def_is_mba23) ; + 48:49 , 0b01 , (def_is_mba01) ; # 0 CNTL , B0_CS2n + 50:51 , 0b01 , (def_is_mba01) ; # 1 CNTL , B0_ODT0 + 52:53 , 0b00 , (def_is_mba01) ; # 2 ADDR , B_WEn + 54:55 , 0b00 , (def_is_mba01) ; # 3 ADDR , B_A2 + 56:57 , 0b01 , (def_is_mba01) ; # 4 CNTL , B0_ODT1 + 58:59 , 0b01 , (def_is_mba01) ; # 5 CNTL , B0_CS0n + 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , B_A3 + 62:63 , 0b00 , (def_is_mba01) ; # 7 ADDR , B_A0 # ----------------- Port 3 ADR 2 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL0 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL1 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL2 - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL3 - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba23) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba23) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba23) ; # CNTL # SEL7 + 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , D0_CS0n + 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , D_A10 + 52:53 , 0b00 , (def_is_mba23) ; # 2 ADDR , D_A4 + 54:55 , 0b01 , (def_is_mba23) ; # 3 CNTL , D1_CS3n + 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , D_ACTn + 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , D_A9 + 60:61 , 0b11 , (def_is_mba23) ; # 6 SPCKE , D1_CKE3 + 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , D1_CKE0 } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2 scom 0x8001482b0301143f { bits , scom_data , expr ; - 48:49 , 0b01 , (def_is_mba01) ; # CNTL # SEL8 clk - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL9 clk - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL10 - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL11 - 56:57 , 0b01 , (def_is_mba01) ; # CNTL # SEL12 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL13 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 2 lanes 8:11 -------------------------------------------- +# B0_CLK1_p, B0_CLK1_n, B_CASn, B1_CS0n, B1_CKE0, B_A12 +# 48:59 , 0xA14 , (def_is_mba01) ; +# ------ PORT 3 ADR 2 lanes 8:11 -------------------------------------------- +# D0_CS3n, D_A2, D1_CLK1_n, D1_CLK1_p, D0_CLK1_n, D0_CLK1_p +# 48:59 , 0x4AA , (def_is_mba23) ; + 48:49 , 0b10 , (def_is_mba01) ; # 8 CLK , B0_CLK1_p + 50:51 , 0b10 , (def_is_mba01) ; # 9 CLK , B0_CLK1_n + 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , B_CASn + 54:55 , 0b01 , (def_is_mba01) ; #11 CNTL , B1_CS0n + 56:57 , 0b01 , (def_is_mba01) ; #12 CNTL , B1_CKE0 + 58:59 , 0b00 , (def_is_mba01) ; #13 ADDR , B_A12 # ----------------- Port 3 ADR 2 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL8 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL9 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL10 clk - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL11 clk - 56:57 , 0b01 , (def_is_mba23) ; # CNTL # SEL12 clk - 58:59 , 0b01 , (def_is_mba23) ; # CNTL # SEL13 clk + 48:49 , 0b01 , (def_is_mba23) ; # 8 CNTL , D0_CS3n + 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , D_A2 + 52:53 , 0b10 , (def_is_mba23) ; #10 CLK , D1_CLK1_n + 54:55 , 0b10 , (def_is_mba23) ; #11 CLK , D1_CLK1_p + 56:57 , 0b10 , (def_is_mba23) ; #12 CLK , D0_CLK1_n + 58:59 , 0b10 , (def_is_mba23) ; #13 CLK , D0_CLK1_p +# 60:63 , 0b0000 , any ; # reserved } # ----------------- Port 1 ADR 3 ----------------------------------------------- # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3 scom 0x80014c2a0301143f { bits , scom_data , expr ; - 48:49 , 0b00 , (def_is_mba01) ; # CMD # SEL0 - 50:51 , 0b01 , (def_is_mba01) ; # CNTL # SEL1 - 52:53 , 0b01 , (def_is_mba01) ; # CNTL # SEL2 clk - 54:55 , 0b01 , (def_is_mba01) ; # CNTL # SEL3 clk - 56:57 , 0b00 , (def_is_mba01) ; # CMD # SEL4 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL5 - 60:61 , 0b01 , (def_is_mba01) ; # CNTL # SEL6 - 62:63 , 0b01 , (def_is_mba01) ; # CNTL # SEL7 +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 3 lanes 0:7 --------------------------------------------- +# B_A11, B0_CKE0, B0_CLK0_n, B0_CLK0_p, B_A13, B_A14, B1_CKE2, B1_ODT0 +# 48:63 , 0x1A0D , (def_is_mba01) ; +# ------ PORT 3 ADR 3 lanes 0:7 --------------------------------------------- +# D1_CS2n, D0_ODT0, D0_CLK0_n, D0_CLK0_p, D_A6, D1_ODT1, D_A0, D_CASn +# 48:63 , 0x5A10 , (def_is_mba23) ; + 48:49 , 0b00 , (def_is_mba01) ; # 0 ADDR , B_A11 + 50:51 , 0b01 , (def_is_mba01) ; # 1 CNTL , B0_CKE0 + 52:53 , 0b10 , (def_is_mba01) ; # 2 CLK , B0_CLK0_n + 54:55 , 0b10 , (def_is_mba01) ; # 3 CLK , B0_CLK0_p + 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , B_A13 + 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , B_A14 + 60:61 , 0b11 , (def_is_mba01) ; # 6 SPCKE , B1_CKE2 + 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , B1_ODT0 # ----------------- Port 3 ADR 3 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # CNTL # SEL0 - 50:51 , 0b01 , (def_is_mba23) ; # CNTL # SEL1 - 52:53 , 0b01 , (def_is_mba23) ; # CNTL # SEL2 clk - 54:55 , 0b01 , (def_is_mba23) ; # CNTL # SEL3 clk - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL4 - 58:59 , 0b01 , (def_is_mba23) ; # CNTL # SEL5 - 60:61 , 0b00 , (def_is_mba23) ; # CMD # SEL6 - 62:63 , 0b00 , (def_is_mba23) ; # CMD # SEL7 + 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , D1_CS2n + 50:51 , 0b01 , (def_is_mba23) ; # 1 CNTL , D0_ODT0 + 52:53 , 0b10 , (def_is_mba23) ; # 2 CLK , D0_CLK0_n + 54:55 , 0b10 , (def_is_mba23) ; # 3 CLK , D0_CLK0_p + 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , D_A6 + 58:59 , 0b01 , (def_is_mba23) ; # 5 CNTL , D1_ODT1 + 60:61 , 0b00 , (def_is_mba23) ; # 6 ADDR , D_A0 + 62:63 , 0b00 , (def_is_mba23) ; # 7 ADDR , D_CASn } # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3 scom 0x80014c2b0301143f { - bits , scom_data , expr ; - 48:49 , 0b00 , (def_is_mba01) ; # CMD # SEL8 - 50:51 , 0b00 , (def_is_mba01) ; # CMD # SEL9 - 52:53 , 0b00 , (def_is_mba01) ; # CMD # SEL10 - 54:55 , 0b00 , (def_is_mba01) ; # CMD # SEL11 - 56:57 , 0b00 , (def_is_mba01) ; # CMD # SEL12 - 58:59 , 0b00 , (def_is_mba01) ; # CMD # SEL13 + bits , scom_data , expr ; # signal +# 0:47 , 0x000000000000, any ; # reserved +# ------ PORT 1 ADR 3 lanes 8:11 -------------------------------------------- +# B_A9, B_BA2, B_RASn, B_ACTn, B_A5, B_PAR +# 48:59 , 0x000 , (def_is_mba01) ; +# ------ PORT 3 ADR 3 lanes 8:11 -------------------------------------------- +# D_A14, D_A3, D_A7, D_A15, D_BA1, D0_CKE2 +# 48:59 , 0x003 , (def_is_mba23) ; + 48:49 , 0b00 , (def_is_mba01) ; # 8 ADDR , B_A9 + 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , B_BA2 + 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , B_RASn + 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , B_ACTn + 56:57 , 0b00 , (def_is_mba01) ; #12 ADDR , B_A5 + 58:59 , 0b00 , (def_is_mba01) ; #13 ADDR , B_PAR # ----------------- Port 3 ADR 3 Map 1 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # CMD # SEL8 - 50:51 , 0b00 , (def_is_mba23) ; # CMD # SEL9 - 52:53 , 0b00 , (def_is_mba23) ; # CMD # SEL10 - 54:55 , 0b00 , (def_is_mba23) ; # CMD # SEL11 - 56:57 , 0b00 , (def_is_mba23) ; # CMD # SEL12 - 58:59 , 0b01 , (def_is_mba23) ; # CNTL # SEL13 + 48:49 , 0b00 , (def_is_mba23) ; # 8 ADDR , D_A14 + 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , D_A3 + 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , D_A7 + 54:55 , 0b00 , (def_is_mba23) ; #11 ADDR , D_A15 + 56:57 , 0b00 , (def_is_mba23) ; #12 ADDR , D_BA1 + 58:59 , 0b11 , (def_is_mba23) ; #13 SPCKE , D0_CKE2 +# 60:63 , 0b0000 , any ; # reserved } # --------------------------------------------------------------------------------------- -# ADR I/O Post Cursor Value Register default=0 !! need to set? -# -# This register contains four Driver Post Cursor Slice values. The registers described in -# Section 5.2.2.7 ADR I/O Post Cursor Value Map {0-1} on page 303 selects which one of -# these four values are sent to each ADR output pin. -# -# The POST_CURSOR* control vectors select the amount of equalization enabled in the address -# drivers. While the vectors determine whether a subset of the slices in each I/O operate -# in either a normal data or post cursor data regime, it is the data history which determines -# the amount of equalization provided at the driver output at any time. -# +# ADR I/O Post Cursor Value Register default=0 not needed anymore # DPHY01_DDRPHY_ADR_IO_POST_CURSOR_VALUE_P0_ADR0 0x018 0x800040180301143f # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_18_L2 # - # --------------------------------------------------------------------------------------- -# ADR I/O Post Cursor Value Map {0-1} Register default=0 !! need to set? -# -# Each predefined pin pair on the ADR can be mapped to one of four Post Cursor values. These -# registers determine which of the four Post Cursor values in the register described in -# Section 5.2.2.6 ADR I/O Post Cursor Value on page 301 are used for the given ADR output pin. -# Pins are defined by the mnemonic {{0-1}*8+n}, with n = 0 - 7, with register 0 containing -# lanes 0:7 and register 1 containing lanes 8:15 -# +# ADR I/O Post Cursor Value Map {0-1} Register default=0 not needed anymore # DPHY01_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0_P0_ADR0 0x028 0x800040280301143f # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_28_L2 -# # --------------------------------------------------------------------------------------- # Centaur Vref Trimmer Control & RCM default=0 !! need to set RCM for DDR3/4 @@ -1639,39 +2354,225 @@ scom 0x80014c2b0301143f { # 0x9 = 0.52750 0x6 = 0.41750 | 0x9 = 0.72750 0x6 = 0.61750 # 0x8 = 0.51375 0x7 = 0.40375 | 0x8 = 0.71375 0x7 = 0.60375 # +# DP18_IO_RX_CONFIG0 # [01:23] P[0:1]_[0:4] # DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0 0x006 0x800000060301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.RCVRPEAK_L2 #scom 0x800(0,1)(00,04,08,0C,10)060301143f { # _P[0:1]_[0:4] -scom 0x800(0,1)3C060301143f { # _P[0:1]_[0:4] via broadcast +scom 0x80003C060301143f { # _P[0:1]_[0:4] via broadcast + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:50 , 0b000 , any ; # PEAK_AMP_CTL_SIDE0, amp ctl bits +# 51 , 0b0 , any ; # reserved, 0=no peaking, [1:7]=0.3dB-0.9dB + 52:54 , 0b000 , any ; # PEAK_AMP_CTL_SIDE1, amp ctl bits +# 55 , 0b0 , any ; # reserved + # SxMCVREF_0_3, Vref trim ctl signals DDR3 DDR4 + 56:59 , 0xF , ((ATTR_EFF_CEN_RD_VREF[0] == 61000) || (ATTR_EFF_CEN_RD_VREF[0] == 81000)) ; + 56:59 , 0xE , ((ATTR_EFF_CEN_RD_VREF[0] == 59625) || (ATTR_EFF_CEN_RD_VREF[0] == 79625)) ; + 56:59 , 0xD , ((ATTR_EFF_CEN_RD_VREF[0] == 58250) || (ATTR_EFF_CEN_RD_VREF[0] == 78250)) ; + 56:59 , 0xC , ((ATTR_EFF_CEN_RD_VREF[0] == 56875) || (ATTR_EFF_CEN_RD_VREF[0] == 76875)) ; + 56:59 , 0xB , ((ATTR_EFF_CEN_RD_VREF[0] == 55500) || (ATTR_EFF_CEN_RD_VREF[0] == 75500)) ; + 56:59 , 0xA , ((ATTR_EFF_CEN_RD_VREF[0] == 54125) || (ATTR_EFF_CEN_RD_VREF[0] == 74125)) ; + 56:59 , 0x9 , ((ATTR_EFF_CEN_RD_VREF[0] == 52750) || (ATTR_EFF_CEN_RD_VREF[0] == 72750)) ; + 56:59 , 0x8 , ((ATTR_EFF_CEN_RD_VREF[0] == 51375) || (ATTR_EFF_CEN_RD_VREF[0] == 71375)) ; + 56:59 , 0x0 , ((ATTR_EFF_CEN_RD_VREF[0] == 50000) || (ATTR_EFF_CEN_RD_VREF[0] == 70000)) ; + 56:59 , 0x1 , ((ATTR_EFF_CEN_RD_VREF[0] == 48625) || (ATTR_EFF_CEN_RD_VREF[0] == 68625)) ; + 56:59 , 0x2 , ((ATTR_EFF_CEN_RD_VREF[0] == 47250) || (ATTR_EFF_CEN_RD_VREF[0] == 67250)) ; + 56:59 , 0x3 , ((ATTR_EFF_CEN_RD_VREF[0] == 45875) || (ATTR_EFF_CEN_RD_VREF[0] == 65875)) ; + 56:59 , 0x4 , ((ATTR_EFF_CEN_RD_VREF[0] == 44500) || (ATTR_EFF_CEN_RD_VREF[0] == 64500)) ; + 56:59 , 0x5 , ((ATTR_EFF_CEN_RD_VREF[0] == 43125) || (ATTR_EFF_CEN_RD_VREF[0] == 63125)) ; + 56:59 , 0x6 , ((ATTR_EFF_CEN_RD_VREF[0] == 41750) || (ATTR_EFF_CEN_RD_VREF[0] == 61750)) ; + 56:59 , 0x7 , ((ATTR_EFF_CEN_RD_VREF[0] == 40375) || (ATTR_EFF_CEN_RD_VREF[0] == 60375)) ; + 56:59 , 0x0 , any ; + 60 , 0b1 , (def_is_ddr4) ; # SxPODVREF, if DDR4, POD=0.7*VDD + 60 , 0b0 , any ; # else (DDR3), POD=0.5*VDD + 61 , 0b0 , any ; # 1=DISABLE_TERMINATION, for dq/dqs pins + # READ_CENTERING_MODE + # (00=MPR_PATTERN_BIT or staggered, custom [01=serial, 10=parallel, 11=custom] using SEQ rd/wr data + 62:63 , 0b11 , def_is_ddr4 ; # for DDR4 + 62:63 , 0b00 , any ; # +} + +scom 0x80013C060301143f { # _P1_[0:4] via broadcast bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:50 , 0b000 , any ; # PEAK_AMP_CTL_SIDE0, amp ctl bits # 51 , 0b0 , any ; # reserved, 0=no peaking, [1:7]=0.3dB-0.9dB 52:54 , 0b000 , any ; # PEAK_AMP_CTL_SIDE1, amp ctl bits # 55 , 0b0 , any ; # reserved # SxMCVREF_0_3, Vref trim ctl signals DDR3 DDR4 - 56:59 , 0xF , ((ATTR_EFF_CEN_RD_VREF == 61000) || (ATTR_EFF_CEN_RD_VREF == 81000)) ; - 56:59 , 0xE , ((ATTR_EFF_CEN_RD_VREF == 59625) || (ATTR_EFF_CEN_RD_VREF == 79625)) ; - 56:59 , 0xD , ((ATTR_EFF_CEN_RD_VREF == 58250) || (ATTR_EFF_CEN_RD_VREF == 78250)) ; - 56:59 , 0xC , ((ATTR_EFF_CEN_RD_VREF == 56875) || (ATTR_EFF_CEN_RD_VREF == 76875)) ; - 56:59 , 0xB , ((ATTR_EFF_CEN_RD_VREF == 55500) || (ATTR_EFF_CEN_RD_VREF == 75500)) ; - 56:59 , 0xA , ((ATTR_EFF_CEN_RD_VREF == 54125) || (ATTR_EFF_CEN_RD_VREF == 74125)) ; - 56:59 , 0x9 , ((ATTR_EFF_CEN_RD_VREF == 52750) || (ATTR_EFF_CEN_RD_VREF == 72750)) ; - 56:59 , 0x8 , ((ATTR_EFF_CEN_RD_VREF == 51375) || (ATTR_EFF_CEN_RD_VREF == 71375)) ; - 56:59 , 0x0 , ((ATTR_EFF_CEN_RD_VREF == 50000) || (ATTR_EFF_CEN_RD_VREF == 70000)) ; - 56:59 , 0x1 , ((ATTR_EFF_CEN_RD_VREF == 48625) || (ATTR_EFF_CEN_RD_VREF == 68625)) ; - 56:59 , 0x2 , ((ATTR_EFF_CEN_RD_VREF == 47250) || (ATTR_EFF_CEN_RD_VREF == 67250)) ; - 56:59 , 0x3 , ((ATTR_EFF_CEN_RD_VREF == 45875) || (ATTR_EFF_CEN_RD_VREF == 65875)) ; - 56:59 , 0x4 , ((ATTR_EFF_CEN_RD_VREF == 44500) || (ATTR_EFF_CEN_RD_VREF == 64500)) ; - 56:59 , 0x5 , ((ATTR_EFF_CEN_RD_VREF == 43125) || (ATTR_EFF_CEN_RD_VREF == 63125)) ; - 56:59 , 0x6 , ((ATTR_EFF_CEN_RD_VREF == 41750) || (ATTR_EFF_CEN_RD_VREF == 61750)) ; - 56:59 , 0x7 , ((ATTR_EFF_CEN_RD_VREF == 40375) || (ATTR_EFF_CEN_RD_VREF == 60375)) ; + 56:59 , 0xF , ((ATTR_EFF_CEN_RD_VREF[1] == 61000) || (ATTR_EFF_CEN_RD_VREF[1] == 81000)) ; + 56:59 , 0xE , ((ATTR_EFF_CEN_RD_VREF[1] == 59625) || (ATTR_EFF_CEN_RD_VREF[1] == 79625)) ; + 56:59 , 0xD , ((ATTR_EFF_CEN_RD_VREF[1] == 58250) || (ATTR_EFF_CEN_RD_VREF[1] == 78250)) ; + 56:59 , 0xC , ((ATTR_EFF_CEN_RD_VREF[1] == 56875) || (ATTR_EFF_CEN_RD_VREF[1] == 76875)) ; + 56:59 , 0xB , ((ATTR_EFF_CEN_RD_VREF[1] == 55500) || (ATTR_EFF_CEN_RD_VREF[1] == 75500)) ; + 56:59 , 0xA , ((ATTR_EFF_CEN_RD_VREF[1] == 54125) || (ATTR_EFF_CEN_RD_VREF[1] == 74125)) ; + 56:59 , 0x9 , ((ATTR_EFF_CEN_RD_VREF[1] == 52750) || (ATTR_EFF_CEN_RD_VREF[1] == 72750)) ; + 56:59 , 0x8 , ((ATTR_EFF_CEN_RD_VREF[1] == 51375) || (ATTR_EFF_CEN_RD_VREF[1] == 71375)) ; + 56:59 , 0x0 , ((ATTR_EFF_CEN_RD_VREF[1] == 50000) || (ATTR_EFF_CEN_RD_VREF[1] == 70000)) ; + 56:59 , 0x1 , ((ATTR_EFF_CEN_RD_VREF[1] == 48625) || (ATTR_EFF_CEN_RD_VREF[1] == 68625)) ; + 56:59 , 0x2 , ((ATTR_EFF_CEN_RD_VREF[1] == 47250) || (ATTR_EFF_CEN_RD_VREF[1] == 67250)) ; + 56:59 , 0x3 , ((ATTR_EFF_CEN_RD_VREF[1] == 45875) || (ATTR_EFF_CEN_RD_VREF[1] == 65875)) ; + 56:59 , 0x4 , ((ATTR_EFF_CEN_RD_VREF[1] == 44500) || (ATTR_EFF_CEN_RD_VREF[1] == 64500)) ; + 56:59 , 0x5 , ((ATTR_EFF_CEN_RD_VREF[1] == 43125) || (ATTR_EFF_CEN_RD_VREF[1] == 63125)) ; + 56:59 , 0x6 , ((ATTR_EFF_CEN_RD_VREF[1] == 41750) || (ATTR_EFF_CEN_RD_VREF[1] == 61750)) ; + 56:59 , 0x7 , ((ATTR_EFF_CEN_RD_VREF[1] == 40375) || (ATTR_EFF_CEN_RD_VREF[1] == 60375)) ; 56:59 , 0x0 , any ; 60 , 0b1 , (def_is_ddr4) ; # SxPODVREF, if DDR4, POD=0.7*VDD 60 , 0b0 , any ; # else (DDR3), POD=0.5*VDD 61 , 0b0 , any ; # 1=DISABLE_TERMINATION, for dq/dqs pins + # READ_CENTERING_MODE # (00=MPR_PATTERN_BIT or staggered, custom [01=serial, 10=parallel, 11=custom] using SEQ rd/wr data - 62:63 , 0b00 , any ; # READ_CENTERING_MODE + 62:63 , 0b11 , def_is_ddr4 ; # for DDR4 + 62:63 , 0b00 , any ; # +} + +#------------------------------------------------------------------------------- +# DDR Vref Output Driver Control register default=0, output to DIMM +# +# ATTR_EFF_DRAM_WR_VREF DDR3 = [420, 425, 430, ... 575] +# Note: NOT valid for DDR4. +# +# Vref driven to the DIMM(s) in 0.5% increments from 0.420 to 0.575. +# Example: VDD=1.5V(nom DDR3), ATTR_EFF_DRAM_WR_VREF = 500, +# Vref = VDD * ATTR_EFF_DRAM_WR_VREF/1000 = 0.750 V +# +# sign bit, VREFDQ[0:3]D +# 01111 = 575+ 01110 = 535 10000 = 495 10001 = 455 +# 00111 = 570 00110 = 530 11000 = 490 11001 = 450 +# 01011 = 565 01010 = 525 10100 = 485 10101 = 445 +# 00011 = 560 00010 = 520 11100 = 480 11101 = 440 +# 01101 = 555 01100 = 515 10010 = 475 10011 = 435 +# 00101 = 550 00100 = 510 11010 = 470 11011 = 430 +# 01001 = 545 01000 = 505 10110 = 465 10111 = 425 +# 00001 = 540 00000 = 500* 11110 = 460 11111 = 420- +# +# [01:23] [0:1] +# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0 0x015 0x8000c0150301143f +scom 0x8000c0150301143f { + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[0] < 500) ; # VREF[0]DQ0 sign bit + 48 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[0] >= 500) ; # VREF[0]DQ0 sign bit + # VREF[0]DQ0D bit enables + 49:52 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[0] == 575) || (ATTR_EFF_DRAM_WR_VREF[0] == 420)) ; + 49:52 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[0] == 570) || (ATTR_EFF_DRAM_WR_VREF[0] == 425)) ; + 49:52 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[0] == 565) || (ATTR_EFF_DRAM_WR_VREF[0] == 430)) ; + 49:52 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[0] == 560) || (ATTR_EFF_DRAM_WR_VREF[0] == 435)) ; + 49:52 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[0] == 555) || (ATTR_EFF_DRAM_WR_VREF[0] == 440)) ; + 49:52 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[0] == 550) || (ATTR_EFF_DRAM_WR_VREF[0] == 445)) ; + 49:52 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[0] == 545) || (ATTR_EFF_DRAM_WR_VREF[0] == 450)) ; + 49:52 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[0] == 540) || (ATTR_EFF_DRAM_WR_VREF[0] == 455)) ; + 49:52 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[0] == 535) || (ATTR_EFF_DRAM_WR_VREF[0] == 460)) ; + 49:52 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[0] == 530) || (ATTR_EFF_DRAM_WR_VREF[0] == 465)) ; + 49:52 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[0] == 525) || (ATTR_EFF_DRAM_WR_VREF[0] == 470)) ; + 49:52 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[0] == 520) || (ATTR_EFF_DRAM_WR_VREF[0] == 475)) ; + 49:52 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[0] == 515) || (ATTR_EFF_DRAM_WR_VREF[0] == 480)) ; + 49:52 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[0] == 510) || (ATTR_EFF_DRAM_WR_VREF[0] == 485)) ; + 49:52 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[0] == 505) || (ATTR_EFF_DRAM_WR_VREF[0] == 490)) ; + 49:52 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[0] == 500) || (ATTR_EFF_DRAM_WR_VREF[0] == 495)) ; + 49:52 , 0b0000 , any ; # VREF[0]DQ0D bit enables + 53 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[0] < 500) ; # VREF[0]DQ1 sign bit + 53 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[0] >= 500) ; # VREF[0]DQ1 sign bit + # VREF[0]DQ1D bit enables + 54:57 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[0] == 575) || (ATTR_EFF_DRAM_WR_VREF[0] == 420)) ; + 54:57 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[0] == 570) || (ATTR_EFF_DRAM_WR_VREF[0] == 425)) ; + 54:57 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[0] == 565) || (ATTR_EFF_DRAM_WR_VREF[0] == 430)) ; + 54:57 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[0] == 560) || (ATTR_EFF_DRAM_WR_VREF[0] == 435)) ; + 54:57 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[0] == 555) || (ATTR_EFF_DRAM_WR_VREF[0] == 440)) ; + 54:57 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[0] == 550) || (ATTR_EFF_DRAM_WR_VREF[0] == 445)) ; + 54:57 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[0] == 545) || (ATTR_EFF_DRAM_WR_VREF[0] == 450)) ; + 54:57 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[0] == 540) || (ATTR_EFF_DRAM_WR_VREF[0] == 455)) ; + 54:57 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[0] == 535) || (ATTR_EFF_DRAM_WR_VREF[0] == 460)) ; + 54:57 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[0] == 530) || (ATTR_EFF_DRAM_WR_VREF[0] == 465)) ; + 54:57 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[0] == 525) || (ATTR_EFF_DRAM_WR_VREF[0] == 470)) ; + 54:57 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[0] == 520) || (ATTR_EFF_DRAM_WR_VREF[0] == 475)) ; + 54:57 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[0] == 515) || (ATTR_EFF_DRAM_WR_VREF[0] == 480)) ; + 54:57 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[0] == 510) || (ATTR_EFF_DRAM_WR_VREF[0] == 485)) ; + 54:57 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[0] == 505) || (ATTR_EFF_DRAM_WR_VREF[0] == 490)) ; + 54:57 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[0] == 500) || (ATTR_EFF_DRAM_WR_VREF[0] == 495)) ; + 54:57 , 0b0000 , any ; +# 58:63 , 0b000000 , any ; # reserved + +# 48:57 , 0x1EF , (ATTR_EFF_DRAM_WR_VREF[0] == 575) ; # 0b 0 1111 0 1111 , 0b01 1110 1111 +# 48:57 , 0x0E7 , (ATTR_EFF_DRAM_WR_VREF[0] == 570) ; # 0b 0 0111 0 0111 , 0b00 1110 0111 +# 48:57 , 0x16B , (ATTR_EFF_DRAM_WR_VREF[0] == 565) ; # 0b 0 1011 0 1011 , 0b01 0110 1011 +# 48:57 , 0x063 , (ATTR_EFF_DRAM_WR_VREF[0] == 560) ; # 0b 0 0011 0 0011 , 0b00 0110 0011 +# 48:57 , 0x1AD , (ATTR_EFF_DRAM_WR_VREF[0] == 555) ; # 0b 0 1101 0 1101 , 0b01 1010 1101 +# 48:57 , 0x0A5 , (ATTR_EFF_DRAM_WR_VREF[0] == 550) ; # 0b 0 0101 0 0101 , 0b00 1010 0101 +# 48:57 , 0x129 , (ATTR_EFF_DRAM_WR_VREF[0] == 545) ; # 0b 0 1001 0 1001 , 0b01 0010 1001 +# 48:57 , 0x029 , (ATTR_EFF_DRAM_WR_VREF[0] == 540) ; # 0b 0 0001 0 0001 , 0b00 0010 0001 +# 48:57 , 0x1CE , (ATTR_EFF_DRAM_WR_VREF[0] == 535) ; # 0b 0 1110 0 1110 , 0b01 1100 1110 +# 48:57 , 0x0C6 , (ATTR_EFF_DRAM_WR_VREF[0] == 530) ; # 0b 0 0110 0 0110 , 0b00 1100 0110 +# 48:57 , 0x14A , (ATTR_EFF_DRAM_WR_VREF[0] == 525) ; # 0b 0 1010 0 1010 , 0b01 0100 1010 +# 48:57 , 0x042 , (ATTR_EFF_DRAM_WR_VREF[0] == 520) ; # 0b 0 0010 0 0010 , 0b00 0100 0010 +# 48:57 , 0x01C , (ATTR_EFF_DRAM_WR_VREF[0] == 515) ; # 0b 0 1100 0 1100 , 0b01 1000 1100 +# 48:57 , 0x004 , (ATTR_EFF_DRAM_WR_VREF[0] == 510) ; # 0b 0 0100 0 0100 , 0b00 1000 0100 +# 48:57 , 0x108 , (ATTR_EFF_DRAM_WR_VREF[0] == 505) ; # 0b 0 1000 0 1000 , 0b01 0000 1000 +# 48:57 , 0x000 , (ATTR_EFF_DRAM_WR_VREF[0] == 500) ; # 0b 0 0000 0 0000 , 0b00 0000 0000 +# 48:57 , 0x210 , (ATTR_EFF_DRAM_WR_VREF[0] == 495) ; # 0b 1 0000 1 0000 , 0b10 0001 0000 +# 48:57 , 0x318 , (ATTR_EFF_DRAM_WR_VREF[0] == 490) ; # 0b 1 1000 1 1000 , 0b11 0001 1000 +# 48:57 , 0x294 , (ATTR_EFF_DRAM_WR_VREF[0] == 485) ; # 0b 1 0100 1 0100 , 0b10 1001 0100 +# 48:57 , 0x39C , (ATTR_EFF_DRAM_WR_VREF[0] == 480) ; # 0b 1 1100 1 1100 , 0b11 1001 1100 +# 48:57 , 0x252 , (ATTR_EFF_DRAM_WR_VREF[0] == 475) ; # 0b 1 0010 1 0010 , 0b10 0101 0010 +# 48:57 , 0x35A , (ATTR_EFF_DRAM_WR_VREF[0] == 470) ; # 0b 1 1010 1 1010 , 0b11 0101 1010 +# 48:57 , 0x2D6 , (ATTR_EFF_DRAM_WR_VREF[0] == 465) ; # 0b 1 0110 1 0110 , 0b10 1101 0110 +# 48:57 , 0x3DE , (ATTR_EFF_DRAM_WR_VREF[0] == 460) ; # 0b 1 1110 1 1110 , 0b11 1101 1110 +# 48:57 , 0x231 , (ATTR_EFF_DRAM_WR_VREF[0] == 455) ; # 0b 1 0001 1 0001 , 0b10 0011 0001 +# 48:57 , 0x339 , (ATTR_EFF_DRAM_WR_VREF[0] == 450) ; # 0b 1 1001 1 1001 , 0b11 0011 1001 +# 48:57 , 0x2B5 , (ATTR_EFF_DRAM_WR_VREF[0] == 445) ; # 0b 1 0101 1 0101 , 0b10 1011 0101 +# 48:57 , 0x3BD , (ATTR_EFF_DRAM_WR_VREF[0] == 440) ; # 0b 1 1101 1 1101 , 0b11 1011 1101 +# 48:57 , 0x273 , (ATTR_EFF_DRAM_WR_VREF[0] == 435) ; # 0b 1 0011 1 0011 , 0b10 0111 0011 +# 48:57 , 0x37B , (ATTR_EFF_DRAM_WR_VREF[0] == 430) ; # 0b 1 1011 1 1011 , 0b11 0111 1011 +# 48:57 , 0x2F7 , (ATTR_EFF_DRAM_WR_VREF[0] == 425) ; # 0b 1 0111 1 0111 , 0b10 1111 0111 +# 48:57 , 0x3FF , (ATTR_EFF_DRAM_WR_VREF[0] == 420) ; # 0b 1 1111 1 1111 , 0b11 1111 1111 +# 58:63 , 0b000000 , any ; # reserved +} +# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1 0x015 0x8001c0150301143f +scom 0x8001c0150301143f { + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[1] < 500) ; # VREF[1]DQ0 sign bit + 48 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[1] >= 500) ; # VREF[1]DQ0 sign bit + # VREF[1]DQ0D bit enables + 49:52 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[1] == 575) || (ATTR_EFF_DRAM_WR_VREF[1] == 420)) ; + 49:52 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[1] == 570) || (ATTR_EFF_DRAM_WR_VREF[1] == 425)) ; + 49:52 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[1] == 565) || (ATTR_EFF_DRAM_WR_VREF[1] == 430)) ; + 49:52 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[1] == 560) || (ATTR_EFF_DRAM_WR_VREF[1] == 435)) ; + 49:52 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[1] == 555) || (ATTR_EFF_DRAM_WR_VREF[1] == 440)) ; + 49:52 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[1] == 550) || (ATTR_EFF_DRAM_WR_VREF[1] == 445)) ; + 49:52 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[1] == 545) || (ATTR_EFF_DRAM_WR_VREF[1] == 450)) ; + 49:52 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[1] == 540) || (ATTR_EFF_DRAM_WR_VREF[1] == 455)) ; + 49:52 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[1] == 535) || (ATTR_EFF_DRAM_WR_VREF[1] == 460)) ; + 49:52 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[1] == 530) || (ATTR_EFF_DRAM_WR_VREF[1] == 465)) ; + 49:52 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[1] == 525) || (ATTR_EFF_DRAM_WR_VREF[1] == 470)) ; + 49:52 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[1] == 520) || (ATTR_EFF_DRAM_WR_VREF[1] == 475)) ; + 49:52 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[1] == 515) || (ATTR_EFF_DRAM_WR_VREF[1] == 480)) ; + 49:52 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[1] == 510) || (ATTR_EFF_DRAM_WR_VREF[1] == 485)) ; + 49:52 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[1] == 505) || (ATTR_EFF_DRAM_WR_VREF[1] == 490)) ; + 49:52 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[1] == 500) || (ATTR_EFF_DRAM_WR_VREF[1] == 495)) ; + 49:52 , 0b0000 , any ; # VREF[1]DQ0D bit enables + 53 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[1] < 500) ; # VREF[1]DQ1 sign bit + 53 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[1] >= 500) ; # VREF[1]DQ1 sign bit + # VREF[1]DQ1D bit enables + 54:57 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[1] == 575) || (ATTR_EFF_DRAM_WR_VREF[1] == 420)) ; + 54:57 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[1] == 570) || (ATTR_EFF_DRAM_WR_VREF[1] == 425)) ; + 54:57 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[1] == 565) || (ATTR_EFF_DRAM_WR_VREF[1] == 430)) ; + 54:57 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[1] == 560) || (ATTR_EFF_DRAM_WR_VREF[1] == 435)) ; + 54:57 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[1] == 555) || (ATTR_EFF_DRAM_WR_VREF[1] == 440)) ; + 54:57 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[1] == 550) || (ATTR_EFF_DRAM_WR_VREF[1] == 445)) ; + 54:57 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[1] == 545) || (ATTR_EFF_DRAM_WR_VREF[1] == 450)) ; + 54:57 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[1] == 540) || (ATTR_EFF_DRAM_WR_VREF[1] == 455)) ; + 54:57 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[1] == 535) || (ATTR_EFF_DRAM_WR_VREF[1] == 460)) ; + 54:57 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[1] == 530) || (ATTR_EFF_DRAM_WR_VREF[1] == 465)) ; + 54:57 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[1] == 525) || (ATTR_EFF_DRAM_WR_VREF[1] == 470)) ; + 54:57 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[1] == 520) || (ATTR_EFF_DRAM_WR_VREF[1] == 475)) ; + 54:57 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[1] == 515) || (ATTR_EFF_DRAM_WR_VREF[1] == 480)) ; + 54:57 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[1] == 510) || (ATTR_EFF_DRAM_WR_VREF[1] == 485)) ; + 54:57 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[1] == 505) || (ATTR_EFF_DRAM_WR_VREF[1] == 490)) ; + 54:57 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[1] == 500) || (ATTR_EFF_DRAM_WR_VREF[1] == 495)) ; + 54:57 , 0b0000 , any ; +# 58:63 , 0b000000 , any ; # reserved } # --------------------------------------------------------------------------------------- @@ -1698,18 +2599,22 @@ scom 0x800(0,1)3C060301143f { # _P[0:1]_[0:4] via broadcast # # [0:1] # DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P0 0x000-0x001 0x8000c4000301143f +# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P0 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.RD_WR_DATA0_L2 scom 0x8000c40(0,1)0301143f { bits , scom_data , expr ; # beat 12345678 - 48:63 , 0x0000 , (def_is_sim) ; # to match dials +# 0:47 , 0x000000000000, any ; # reserved +# 48:63 , 0x0000 , (def_is_sim) ; # to match dials 48:63 , 0x5555 , any ; # MPR_PATTERN_BIT of 0F0F0F0F pattern # 48:63 , 0xD896 , any ; # 1st half-nibble of EA0CA653 pattern } -# DPHY01_DDRPHY_SEQ_RD_WR_DATA[0:1]_P1 +# DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P1 +# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P1 scom 0x8001c40(0,1)0301143f { bits , scom_data , expr ; # beat 12345678 - 48:63 , 0x0000 , (def_is_sim) ; # to match dials +# 0:47 , 0x000000000000, any ; # reserved +# 48:63 , 0x0000 , (def_is_sim) ; # to match dials 48:63 , 0x5555 , any ; # MPR_PATTERN_BIT of 0F0F0F0F pattern # 48:63 , 0xCD03 , any ; # 2st half-nibble of EA0CA653 pattern } @@ -1750,117 +2655,6 @@ scom 0x8001c40(0,1)0301143f { # #------------------------------------------------------------------------------- -# DDR Vref Output Driver Control register default=0, output to DIMM -# -# ATTR_EFF_DRAM_WR_VREF DDR3 = [420, 425, 430, ... 575] -# Note: NOT valid for DDR4. -# -# Vref driven to the DIMM(s) in 0.5% increments from 0.420 to 0.575. -# Example: VDD=1.5V(nom DDR3), ATTR_EFF_DRAM_WR_VREF = 500, -# Vref = VDD * ATTR_EFF_DRAM_WR_VREF/1000 = 0.750 V -# -# sign bit, VREFDQ[0:3]D -# 01111 = 575+ 01110 = 535 10000 = 495 10001 = 455 -# 00111 = 570 00110 = 530 11000 = 490 11001 = 450 -# 01011 = 565 01010 = 525 10100 = 485 10101 = 445 -# 00011 = 560 00010 = 520 11100 = 480 11101 = 440 -# 01101 = 555 01100 = 515 10010 = 475 10011 = 435 -# 00101 = 550 00100 = 510 11010 = 470 11011 = 430 -# 01001 = 545 01000 = 505 10110 = 465 10111 = 425 -# 00001 = 540 00000 = 500* 11110 = 460 11111 = 420- -# -# [01:23] [0:1] -# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0 0x015 0x8000c0150301143f -scom 0x8000c0150301143f { - bits , scom_data , expr ; - 48 , 0b1 , (ATTR_EFF_DRAM_WR_VREF < 500) ; # VREFDQ0 sign bit - 48 , 0b0 , (ATTR_EFF_DRAM_WR_VREF >= 500) ; # VREFDQ0 sign bit - # VREFDQ0D bit enables - 49:52 , 0xF , ((ATTR_EFF_DRAM_WR_VREF == 575) || (ATTR_EFF_DRAM_WR_VREF == 420)) ; - 49:52 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF == 570) || (ATTR_EFF_DRAM_WR_VREF == 425)) ; - 49:52 , 0xB , ((ATTR_EFF_DRAM_WR_VREF == 565) || (ATTR_EFF_DRAM_WR_VREF == 430)) ; - 49:52 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF == 560) || (ATTR_EFF_DRAM_WR_VREF == 435)) ; - 49:52 , 0xD , ((ATTR_EFF_DRAM_WR_VREF == 555) || (ATTR_EFF_DRAM_WR_VREF == 440)) ; - 49:52 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF == 550) || (ATTR_EFF_DRAM_WR_VREF == 445)) ; - 49:52 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF == 545) || (ATTR_EFF_DRAM_WR_VREF == 450)) ; - 49:52 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF == 540) || (ATTR_EFF_DRAM_WR_VREF == 455)) ; - 49:52 , 0xE , ((ATTR_EFF_DRAM_WR_VREF == 535) || (ATTR_EFF_DRAM_WR_VREF == 460)) ; - 49:52 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF == 530) || (ATTR_EFF_DRAM_WR_VREF == 465)) ; - 49:52 , 0xA , ((ATTR_EFF_DRAM_WR_VREF == 525) || (ATTR_EFF_DRAM_WR_VREF == 470)) ; - 49:52 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF == 520) || (ATTR_EFF_DRAM_WR_VREF == 475)) ; - 49:52 , 0xC , ((ATTR_EFF_DRAM_WR_VREF == 515) || (ATTR_EFF_DRAM_WR_VREF == 480)) ; - 49:52 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF == 510) || (ATTR_EFF_DRAM_WR_VREF == 485)) ; - 49:52 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF == 505) || (ATTR_EFF_DRAM_WR_VREF == 490)) ; - 49:52 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF == 500) || (ATTR_EFF_DRAM_WR_VREF == 495)) ; - 49:52 , 0b0000 , any ; # VREFDQ0D bit enables - 53 , 0b1 , (ATTR_EFF_DRAM_WR_VREF < 500) ; # VREFDQ1 sign bit - 53 , 0b0 , (ATTR_EFF_DRAM_WR_VREF >= 500) ; # VREFDQ1 sign bit - # VREFDQ1D bit enables - 54:57 , 0xF , ((ATTR_EFF_DRAM_WR_VREF == 575) || (ATTR_EFF_DRAM_WR_VREF == 420)) ; - 54:57 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF == 570) || (ATTR_EFF_DRAM_WR_VREF == 425)) ; - 54:57 , 0xB , ((ATTR_EFF_DRAM_WR_VREF == 565) || (ATTR_EFF_DRAM_WR_VREF == 430)) ; - 54:57 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF == 560) || (ATTR_EFF_DRAM_WR_VREF == 435)) ; - 54:57 , 0xD , ((ATTR_EFF_DRAM_WR_VREF == 555) || (ATTR_EFF_DRAM_WR_VREF == 440)) ; - 54:57 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF == 550) || (ATTR_EFF_DRAM_WR_VREF == 445)) ; - 54:57 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF == 545) || (ATTR_EFF_DRAM_WR_VREF == 450)) ; - 54:57 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF == 540) || (ATTR_EFF_DRAM_WR_VREF == 455)) ; - 54:57 , 0xE , ((ATTR_EFF_DRAM_WR_VREF == 535) || (ATTR_EFF_DRAM_WR_VREF == 460)) ; - 54:57 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF == 530) || (ATTR_EFF_DRAM_WR_VREF == 465)) ; - 54:57 , 0xA , ((ATTR_EFF_DRAM_WR_VREF == 525) || (ATTR_EFF_DRAM_WR_VREF == 470)) ; - 54:57 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF == 520) || (ATTR_EFF_DRAM_WR_VREF == 475)) ; - 54:57 , 0xC , ((ATTR_EFF_DRAM_WR_VREF == 515) || (ATTR_EFF_DRAM_WR_VREF == 480)) ; - 54:57 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF == 510) || (ATTR_EFF_DRAM_WR_VREF == 485)) ; - 54:57 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF == 505) || (ATTR_EFF_DRAM_WR_VREF == 490)) ; - 54:57 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF == 500) || (ATTR_EFF_DRAM_WR_VREF == 495)) ; - 54:57 , 0b0000 , any ; -# 58:63 , 0b000000 , any ; # reserved - -# sign bit, VREFDQ[0:3]D -# 01111 = 575+ 01110 = 535 10000 = 495 10001 = 455 -# 00111 = 570 00110 = 530 11000 = 490 11001 = 450 -# 01011 = 565 01010 = 525 10100 = 485 10101 = 445 -# 00011 = 560 00010 = 520 11100 = 480 11101 = 440 -# 01101 = 555 01100 = 515 10010 = 475 10011 = 435 -# 00101 = 550 00100 = 510 11010 = 470 11011 = 430 -# 01001 = 545 01000 = 505 10110 = 465 10111 = 425 -# 00001 = 540 00000 = 500* 11110 = 460 11111 = 420- -# -# D0SIGN, D0ENA, D1SIGN, D1ENA -# 48:57 , 0x1EF , (ATTR_EFF_DRAM_WR_VREF == 575) ; # 0b 0 1111 0 1111 , 0b01 1110 1111 -# 48:57 , 0x0E7 , (ATTR_EFF_DRAM_WR_VREF == 570) ; # 0b 0 0111 0 0111 , 0b00 1110 0111 -# 48:57 , 0x16B , (ATTR_EFF_DRAM_WR_VREF == 565) ; # 0b 0 1011 0 1011 , 0b01 0110 1011 -# 48:57 , 0x063 , (ATTR_EFF_DRAM_WR_VREF == 560) ; # 0b 0 0011 0 0011 , 0b00 0110 0011 -# 48:57 , 0x1AD , (ATTR_EFF_DRAM_WR_VREF == 555) ; # 0b 0 1101 0 1101 , 0b01 1010 1101 -# 48:57 , 0x0A5 , (ATTR_EFF_DRAM_WR_VREF == 550) ; # 0b 0 0101 0 0101 , 0b00 1010 0101 -# 48:57 , 0x129 , (ATTR_EFF_DRAM_WR_VREF == 545) ; # 0b 0 1001 0 1001 , 0b01 0010 1001 -# 48:57 , 0x029 , (ATTR_EFF_DRAM_WR_VREF == 540) ; # 0b 0 0001 0 0001 , 0b00 0010 0001 -# 48:57 , 0x1CE , (ATTR_EFF_DRAM_WR_VREF == 535) ; # 0b 0 1110 0 1110 , 0b01 1100 1110 -# 48:57 , 0x0C6 , (ATTR_EFF_DRAM_WR_VREF == 530) ; # 0b 0 0110 0 0110 , 0b00 1100 0110 -# 48:57 , 0x14A , (ATTR_EFF_DRAM_WR_VREF == 525) ; # 0b 0 1010 0 1010 , 0b01 0100 1010 -# 48:57 , 0x042 , (ATTR_EFF_DRAM_WR_VREF == 520) ; # 0b 0 0010 0 0010 , 0b00 0100 0010 -# 48:57 , 0x01C , (ATTR_EFF_DRAM_WR_VREF == 515) ; # 0b 0 1100 0 1100 , 0b01 1000 1100 -# 48:57 , 0x004 , (ATTR_EFF_DRAM_WR_VREF == 510) ; # 0b 0 0100 0 0100 , 0b00 1000 0100 -# 48:57 , 0x108 , (ATTR_EFF_DRAM_WR_VREF == 505) ; # 0b 0 1000 0 1000 , 0b01 0000 1000 -# 48:57 , 0x000 , (ATTR_EFF_DRAM_WR_VREF == 500) ; # 0b 0 0000 0 0000 , 0b00 0000 0000 -# 48:57 , 0x210 , (ATTR_EFF_DRAM_WR_VREF == 495) ; # 0b 1 0000 1 0000 , 0b10 0001 0000 -# 48:57 , 0x318 , (ATTR_EFF_DRAM_WR_VREF == 490) ; # 0b 1 1000 1 1000 , 0b11 0001 1000 -# 48:57 , 0x294 , (ATTR_EFF_DRAM_WR_VREF == 485) ; # 0b 1 0100 1 0100 , 0b10 1001 0100 -# 48:57 , 0x39C , (ATTR_EFF_DRAM_WR_VREF == 480) ; # 0b 1 1100 1 1100 , 0b11 1001 1100 -# 48:57 , 0x252 , (ATTR_EFF_DRAM_WR_VREF == 475) ; # 0b 1 0010 1 0010 , 0b10 0101 0010 -# 48:57 , 0x35A , (ATTR_EFF_DRAM_WR_VREF == 470) ; # 0b 1 1010 1 1010 , 0b11 0101 1010 -# 48:57 , 0x2D6 , (ATTR_EFF_DRAM_WR_VREF == 465) ; # 0b 1 0110 1 0110 , 0b10 1101 0110 -# 48:57 , 0x3DE , (ATTR_EFF_DRAM_WR_VREF == 460) ; # 0b 1 1110 1 1110 , 0b11 1101 1110 -# 48:57 , 0x231 , (ATTR_EFF_DRAM_WR_VREF == 455) ; # 0b 1 0001 1 0001 , 0b10 0011 0001 -# 48:57 , 0x339 , (ATTR_EFF_DRAM_WR_VREF == 450) ; # 0b 1 1001 1 1001 , 0b11 0011 1001 -# 48:57 , 0x2B5 , (ATTR_EFF_DRAM_WR_VREF == 445) ; # 0b 1 0101 1 0101 , 0b10 1011 0101 -# 48:57 , 0x3BD , (ATTR_EFF_DRAM_WR_VREF == 440) ; # 0b 1 1101 1 1101 , 0b11 1011 1101 -# 48:57 , 0x273 , (ATTR_EFF_DRAM_WR_VREF == 435) ; # 0b 1 0011 1 0011 , 0b10 0111 0011 -# 48:57 , 0x37B , (ATTR_EFF_DRAM_WR_VREF == 430) ; # 0b 1 1011 1 1011 , 0b11 0111 1011 -# 48:57 , 0x2F7 , (ATTR_EFF_DRAM_WR_VREF == 425) ; # 0b 1 0111 1 0111 , 0b10 1111 0111 -# 48:57 , 0x3FF , (ATTR_EFF_DRAM_WR_VREF == 420) ; # 0b 1 1111 1 1111 , 0b11 1111 1111 -} - -#------------------------------------------------------------------------------- # ODT Default Configuration Register # # Determines the ODT values sent to all ranks during MRS commands @@ -1887,24 +2681,28 @@ scom 0x8000c0150301143f { scom 0x8000C40E0301143F { # ODT 01234567 bits , scom_data ; # DIMM0, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[0][0][0] ; # when Read of Rank0 56:63 , ATTR_EFF_ODT_RD[0][0][1] ; # when Read of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 scom 0x8000C40F0301143F { bits , scom_data ; # DIMM0, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[0][0][2] ; # when Read of Rank2 56:63 , ATTR_EFF_ODT_RD[0][0][3] ; # when Read of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P0 scom 0x8000C4100301143F { bits , scom_data ; # DIMM1, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[0][1][0] ; # when Read of Rank4 56:63 , ATTR_EFF_ODT_RD[0][1][1] ; # when Read of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P0 scom 0x8000C4110301143F { bits , scom_data ; # DIMM1, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[0][1][2] ; # when Read of Rank6 56:63 , ATTR_EFF_ODT_RD[0][1][3] ; # when Read of Rank7 } @@ -1912,24 +2710,28 @@ scom 0x8000C4110301143F { # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG0_P1 scom 0x8001C40E0301143F { bits , scom_data ; # DIMM2, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[1][0][0] ; # when Read of Rank0 56:63 , ATTR_EFF_ODT_RD[1][0][1] ; # when Read of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P1 scom 0x8001C40F0301143F { bits , scom_data ; # DIMM2, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[1][0][2] ; # when Read of Rank2 56:63 , ATTR_EFF_ODT_RD[1][0][3] ; # when Read of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P1 scom 0x8001C4100301143F { bits , scom_data ; # DIMM3, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[1][1][0] ; # when Read of Rank4 56:63 , ATTR_EFF_ODT_RD[1][1][1] ; # when Read of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P1 scom 0x8001C4110301143F { bits , scom_data ; # DIMM3, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_RD[1][1][2] ; # when Read of Rank6 56:63 , ATTR_EFF_ODT_RD[1][1][3] ; # when Read of Rank7 } @@ -1943,24 +2745,28 @@ scom 0x8001C4110301143F { # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.ODT_WR_CONFIG0_L2 scom 0x8000C40A0301143F { bits , scom_data ; # DIMM0, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[0][0][0] ; # when write of Rank0 56:63 , ATTR_EFF_ODT_WR[0][0][1] ; # when write of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 scom 0x8000C40B0301143F { bits , scom_data ; # DIMM0, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[0][0][2] ; # when write of Rank2 56:63 , ATTR_EFF_ODT_WR[0][0][3] ; # when write of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P0 scom 0x8000C40C0301143F { bits , scom_data ; # DIMM1, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[0][1][0] ; # when write of Rank4 56:63 , ATTR_EFF_ODT_WR[0][1][1] ; # when write of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P0 scom 0x8000C40D0301143F { bits , scom_data ; # DIMM1, Port0 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[0][1][2] ; # when write of Rank6 56:63 , ATTR_EFF_ODT_WR[0][1][3] ; # when write of Rank7 } @@ -1968,24 +2774,28 @@ scom 0x8000C40D0301143F { # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG0_P1 scom 0x8001C40A0301143F { bits , scom_data ; # DIMM2, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[1][0][0] ; # when write of Rank0 56:63 , ATTR_EFF_ODT_WR[1][0][1] ; # when write of Rank1 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P1 scom 0x8001C40B0301143F { bits , scom_data ; # DIMM2, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[1][0][2] ; # when write of Rank2 56:63 , ATTR_EFF_ODT_WR[1][0][3] ; # when write of Rank3 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P1 scom 0x8001C40C0301143F { bits , scom_data ; # DIMM3, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[1][1][0] ; # when write of Rank4 56:63 , ATTR_EFF_ODT_WR[1][1][1] ; # when write of Rank5 } # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P1 scom 0x8001C40D0301143F { bits , scom_data ; # DIMM3, Port1 +# 0:47 , 0x000000000000 ; # reserved 48:55 , ATTR_EFF_ODT_WR[1][1][2] ; # when write of Rank6 56:63 , ATTR_EFF_ODT_WR[1][1][3] ; # when write of Rank7 } @@ -1995,46 +2805,13 @@ scom 0x8001C40D0301143F { # # DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0 0x01C 0x8000c01c0301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG28_RP0_L2 -# -# ~~~~~~~~~~~~ Mode Register settings ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# -- MR0 -- DDRPHY_PC_MR0_PRI_RP[0:3]_P[0:1] 0x01C 0x8000c01c0301143f -# ATTR_EFF_DRAM_DLL_PPD # 0=slow exit, 1=fast exit -# ATTR_EFF_DRAM_WR -# ATTR_EFF_DRAM_DLL_RESET # 0=no, 1=yes -# ATTR_EFF_DRAM_TM # 0=normal, 1= Test -# ATTR_EFF_DRAM_CL -# ATTR_EFF_DRAM_RBT # 0=sequential, 1=interleave -# ATTR_EFF_DRAM_BL # 0=BL8, OTF=1, BC4=2 -# -- MR1 -- DDRPHY_PC_MR1_PRI_RP[0:3]_P[0:1] 0x01D 0x8000c01d0301143f -# ATTR_EFF_DRAM_OUTPUT_BUFFER # 0=enable, 1=disable -# ATTR_EFF_DRAM_TDQS # 0=disable, 1=enable -# ATTR_EFF_DRAM_RTT_NOM [0..1][0..1][0..3] # 0, 20, 30, 34(DDR4), 40, 48(DDR4), 50, 80(DDR4), 120, 240(DDR4) -# ATTR_EFF_DRAM_WR_LVL_ENABLE # 0=disable, 1=enable -# ATTR_EFF_DRAM_RON [0..1][0..1] # 34, 40(DDR3) -# ATTR_EFF_DRAM_AL # 0=disable, 1=CL-1, 2=CL-2 -# ATTR_EFF_DRAM_DLL_ENABLE # 0=enable 1=disable -# -- MR2 -- DDRPHY_PC_MR2_PRI_RP[0:3]_P[0:1] 0x01E 0x8000c01e0301143f -# ATTR_EFF_DRAM_RTT_WR [0..1][0..1][0..3] # 0, 60, 120 -# ATTR_EFF_DRAM_SRT # 0=normal, 1=extend -# ATTR_EFF_DRAM_ASR # 0=SRT, 1=ASR -# ATTR_EFF_DRAM_CWL -# ATTR_EFF_DRAM_PASR # 0=full, 1=1st 1/2, 2=1st 1/4, 3=1st 1/8, 4=last 3/4, 5=last 1/2, 6=last 1/4, 7=last 1/8 -# -- MR3 -- DDRPHY_PC_MR3_PRI_RP[0:3]_P[0:1] 0x01F 0x8000c01f0301143f -# ATTR_EFF_MPR_MODE # 0=disable, 1=enable -# ATTR_EFF_MPR_LOC -# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# -# ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15 [0..1][0..1] uint64 -# -# RCD_LRDIM_CNTL_WORD0_15Q 0x000000dd -# CWD=BA1,BA0,A4,A3 0:3=CWD0, 4:7=CWD1, 8:11=CWD2, etc. -# last RCD or LRDIMM control word that was programmed using CCS. # --------------------------------------------------------------------------------------- -# PC Chip select ID configuration register default=0 !! need to set? +# PC Chip select ID configuration register default=0 NEED to be programmed for DDR4/TSV dimms. +# HERE MW # # This register controls the value of Chip Select (CS) signals not selected -# by any of the PC Rank Pair registers during initial calibration. +# by any of the PC Rank Pair registers during initial calibration for DDR4 / TSV dimms. # # DPHY01_DDRPHY_PC_CSID_CFG_P0 0x033 0x8000c0330301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG51_L2 @@ -2062,6 +2839,7 @@ scom 0x8001C40D0301143F { # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.DQSOFFSET_L2(0:6) scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved # 48 , 0b0 , any ; # reserved # 49:55 , 0b0010000 , (def_is_sim) ; # DQS_OFFSET 49:55 , def_dqs_offset , any ; # DQS_OFFSET, 7 bits @@ -2090,6 +2868,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # _RP[0:3]_P[0:1]_[0:4], all instances and rank pairs via broadcast, both ports # scom 0x800(0,1)3CFE0301143f { # _RP[0:3]_P[0:1]_[0:4] # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # 48:51 , 0x0 , any ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , any ; # DQ_WR_OFFSET_N1 # 56:59 , 0x0 , any ; # DQ_WR_OFFSET_N2 @@ -2098,6 +2877,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # # scom 0x80003C7E0301143f { # _RP0_P0_[0:4], rank pair 0, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2111,6 +2891,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # scom 0x80003D7E0301143f { # _RP1_P0_[0:4], rank pair 1, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2124,6 +2905,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # scom 0x80003E7E0301143f { # _RP2_P0_[0:4], rank pair 2, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2137,6 +2919,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # scom 0x80003F7E0301143f { # _RP3_P0_[0:4], rank pair 3, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2151,6 +2934,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # =============================================================================== # scom 0x80013C7E0301143f { # _RP0_P1_[0:4], rank pair 0, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2164,6 +2948,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # scom 0x80013D7E0301143f { # _RP1_P1_[0:4], rank pair 1, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2177,6 +2962,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # scom 0x80013E7E0301143f { # _RP2_P1_[0:4], rank pair 2, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2190,6 +2976,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # scom 0x80013F7E0301143f { # _RP3_P1_[0:4], rank pair 3, all instances via broadcast # bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ # 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 # 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 @@ -2203,7 +2990,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # } # --------------------------------------------------------------------------------------- -# DP18 Write Delay Value {0-23} Register default=0x0008 !! need to set this? +# DP18 Write Delay Value {0-23} Register default=0x0008 !! set after characterization # # Attributes # Read/Write via programming interface. Write via hardware. @@ -2223,7 +3010,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # # --------------------------------------------------------------------------------------- -# DP18 Read Delay Value {0-11} Register default=0x4040 !! need to set this? +# DP18 Read Delay Value {0-11} Register default=0x4040 !! characterization req'd # # Attributes # Read/Write via programming interface. Write via hardware. Each register holds the delay value @@ -2241,7 +3028,7 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # # --------------------------------------------------------------------------------------- -# DP18 Drift Limits Register default=0 !! need to set this? +# DP18 Drift Limits Register default=0 !! set after characterization # # Description # This register holds the limits for periodic drift of the data eye and the received strobe. @@ -2249,6 +3036,8 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # DPHY01_DDRPHY_DP18_DRIFT_LIMITS_P0_0 0x00A 0x8000000a0301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.LIMITS_L2 # +# min_rd_eye_size, max_dqs_drift +# 0 disables check # --------------------------------------------------------------------------------------- # DP18 DQS Gate Delay Register default=0 !! need to set this? @@ -2286,19 +3075,20 @@ scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG22_L2 scom 0x8000C0160301143F { # Port 0 bits , scom_data , expr ; - 48 , 0b1 , (def_is_sim) ; # ENA_WR_LEVEL - 49 , 0b0 , (def_is_sim) ; # ENA_INITIAL_PAT_WR, for custom pattern - 50 , 0b1 , (def_is_sim) ; # ENA_DQS_ALIGN - 51 , 0b1 , (def_is_sim) ; # ENA_RDCLK_ALIGN +# 0:47 , 0x000000000000, any ; # reserved + 48 , 0b1 , any ; # ENA_WR_LEVEL + 49 , 0b0 , any ; # ENA_INITIAL_PAT_WR, for custom pattern + 50 , 0b1 , any ; # ENA_DQS_ALIGN + 51 , 0b1 , any ; # ENA_RDCLK_ALIGN - 52 , 0b1 , (def_is_sim) ; # ENA_READ_CTR - 53 , 0b1 , (def_is_sim) ; # ENA_WRITE_CTR - 54 , 0b1 , (def_is_sim) ; # ENA_INITIAL_COARSE_WR - 55 , 0b1 , (def_is_sim) ; # ENA_COARSE_RD + 52 , 0b1 , any ; # ENA_READ_CTR + 53 , 0b1 , any ; # ENA_WRITE_CTR + 54 , 0b1 , any ; # ENA_INITIAL_COARSE_WR + 55 , 0b1 , any ; # ENA_COARSE_RD 56 , 0b0 , any ; # ENA_CUSTOM_RD 57 , 0b0 , any ; # ENA_CUSTOM_WR - 58 , 0b1 , (def_is_sim) ; # ABORT_ON_CAL_ERROR + 58 , 0b1 , any ; # ABORT_ON_CAL_ERROR 59 , 0b0 , any ; # ENA_DIGITAL_EYE # ENA_RANK_GROUP[0:3], 4 bits @@ -2315,6 +3105,7 @@ scom 0x8000C0160301143F { # Port 0 # DPHY01.DDRPHY_PC_INIT_CAL_CONFIG0_P1 scom 0x8001C0160301143F { # Port 1 bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48 , 0b1 , (def_is_sim) ; # ENA_WR_LEVEL 49 , 0b0 , (def_is_sim) ; # ENA_INITIAL_PAT_WR, for custom pattern 50 , 0b1 , (def_is_sim) ; # ENA_DQS_ALIGN @@ -2340,23 +3131,35 @@ scom 0x8001C0160301143F { # Port 1 # --------------------------------------------------------------------------------------- # Initial calibration sequence Config1 register default=0 +# EFF_DRAM_TRFI # # Controls refreshes during calibration, and regular refresh interval. -# !! Needed? Does a procedure do this? -# -# EFF_DRAM_TRFI +# if DDR3/4 with custom pattern then need refresh since pattern written into memory +# +# REFRESH_CONTROL { 00 = Refresh commands are only sent at start of initial calibration, +# based on the value in the .REFRESH_COUNT. field. Disables if count=0 +# 01 = Use the internal Refresh Interval timer to determine when refresh +# commands are sent; allow refreshes to occur between calibration routines. +# 10 = Reserved +# 11 = Use the internal Refresh Interval timer to determine when refresh +# commands should be sent; in addition to allowing refreshes commands to be +# issued between calibration routines, also allow refreshes to interrupt each +# calibration routine (as required). This is the recommended setting when +# refreshes are required during initial calibration. +# } # # DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P0 0x017 0x8000c0170301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG23_L2 scom 0x800(0,1)C0170301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:51 , 0b0000 , any ; # REFRESH_COUNT, num of refreshes before cal 52:53 , 0b00 , any ; # REFRESH_CONTROL during initial calibration 54 , 0b0 , any ; # REFRESH_ALL_RANKS, during calibration # 55:56 , 0b00 , any ; # reserved # REFRESH_INTERVAL, defaults to 6 if value < 6, value*256=num clks between refreshes # ATTR_EFF_DRAM_TRFI = refresh interval in clocks - 57:63 , 0b0000000 , (def_is_sim) ; # match dials +# 57:63 , 0b0000000 , (def_is_sim) ; # match dials 57:63 , (ATTR_EFF_DRAM_TRFI >> 8) , any ; # field needs refresh/256 } @@ -2368,53 +3171,57 @@ scom 0x800(0,1)C0170301143F { # _P[0:1] # DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0 0x00B 0x8000c00b0301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG11_L2 scom 0x8000C00B0301143F { # Port 0 - bits , scom_data , expr ; + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # PER_ENA_RANK_GROUP[0:3], 4 bits - 48 , 0b1 , (def_val_prg0_p0) ; # enable primary rank group 0 - 48 , 0b0 , any ; # disable primary rank group 0 - 49 , 0b1 , (def_val_prg1_p0) ; # enable primary rank group 1 - 49 , 0b0 , any ; # disable primary rank group 1 - 50 , 0b1 , (def_val_prg2_p0) ; # enable primary rank group 2 - 50 , 0b0 , any ; # disable primary rank group 2 - 51 , 0b1 , (def_val_prg3_p0) ; # enable primary rank group 3 - 51 , 0b0 , any ; # disable primary rank group 3 - - 52 , 0b1 , any ; # PER_ENA_ZCAL - 53 , 0b1 , any ; # PER_ENA_SYSCLK_ALIGN - 54 , 0b1 , any ; # ENA_PER_RDCLK_ALIGN - 55 , 0b1 , any ; # ENA_PER_DQS_ALIGN - 56 , 0b1 , any ; # ENA_PER_READ_CTR - 57:58 , 0b00 , any ; # PER_NEXT_RANK_group - 59 , 0b1 , any ; # FAST_SIM_PER_CNTR - 60 , 0b0 , any ; # START_INIT_CAL - 61 , 0b0 , any ; # START_PER_CAL - 62 , 0b0 , any ; # ABORT_ON_ERR_EN - 63 , 0b0 , any ; # ZCAL_UPDATE_MODE + 48 , 0b1 , (def_val_prg0_p0) ; # enable primary rank group 0 + 48 , 0b0 , any ; # disable primary rank group 0 + 49 , 0b1 , (def_val_prg1_p0) ; # enable primary rank group 1 + 49 , 0b0 , any ; # disable primary rank group 1 + 50 , 0b1 , (def_val_prg2_p0) ; # enable primary rank group 2 + 50 , 0b0 , any ; # disable primary rank group 2 + 51 , 0b1 , (def_val_prg3_p0) ; # enable primary rank group 3 + 51 , 0b0 , any ; # disable primary rank group 3 + + 52 , 0b1 , any ; # PER_ENA_ZCAL + 53 , 0b1 , any ; # PER_ENA_SYSCLK_ALIGN + 54 , 0b1 , any ; # ENA_PER_RDCLK_ALIGN + 55 , 0b1 , any ; # ENA_PER_DQS_ALIGN + 56 , 0b1 , any ; # ENA_PER_READ_CTR + 57:58 , 0b00 , any ; # PER_NEXT_RANK_PAIR + 59 , 0b1 , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR + 59 , 0b0 , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR + 60 , 0b0 , any ; # START_INIT_CAL + 61 , 0b0 , any ; # START_PER_CAL + 62 , 0b0 , any ; # ABORT_ON_ERR_EN + 63 , 0b0 , any ; # ZCAL_UPDATE_MODE } # DPHY01.DDRPHY_PC_PER_CAL_CONFIG_P1 scom 0x8001C00B0301143F { # Port 1 - bits , scom_data , expr ; + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # PER_ENA_RANK_GROUP[0:3], 4 bits - 48 , 0b1 , (def_val_prg0_p1) ; # enable primary rank group 0 - 48 , 0b0 , any ; # disable primary rank group 0 - 49 , 0b1 , (def_val_prg1_p1) ; # enable primary rank group 1 - 49 , 0b0 , any ; # disable primary rank group 1 - 50 , 0b1 , (def_val_prg2_p1) ; # enable primary rank group 2 - 50 , 0b0 , any ; # disable primary rank group 2 - 51 , 0b1 , (def_val_prg3_p1) ; # enable primary rank group 3 - 51 , 0b0 , any ; # disable primary rank group 3 - - 52 , 0b1 , any ; # PER_ENA_ZCAL - 53 , 0b1 , any ; # PER_ENA_SYSCLK_ALIGN - 54 , 0b1 , any ; # ENA_PER_RDCLK_ALIGN - 55 , 0b1 , any ; # ENA_PER_DQS_ALIGN - 56 , 0b1 , any ; # ENA_PER_READ_CTR - 57:58 , 0b00 , any ; # PER_NEXT_RANK_PAIR - 59 , 0b1 , any ; # FAST_SIM_PER_CNTR - 60 , 0b0 , any ; # START_INIT_CAL - 61 , 0b0 , any ; # START_PER_CAL - 62 , 0b0 , any ; # ABORT_ON_ERR_EN - 63 , 0b0 , any ; # ZCAL_UPDATE_MODE + 48 , 0b1 , (def_val_prg0_p1) ; # enable primary rank group 0 + 48 , 0b0 , any ; # disable primary rank group 0 + 49 , 0b1 , (def_val_prg1_p1) ; # enable primary rank group 1 + 49 , 0b0 , any ; # disable primary rank group 1 + 50 , 0b1 , (def_val_prg2_p1) ; # enable primary rank group 2 + 50 , 0b0 , any ; # disable primary rank group 2 + 51 , 0b1 , (def_val_prg3_p1) ; # enable primary rank group 3 + 51 , 0b0 , any ; # disable primary rank group 3 + + 52 , 0b1 , any ; # PER_ENA_ZCAL + 53 , 0b1 , any ; # PER_ENA_SYSCLK_ALIGN + 54 , 0b1 , any ; # ENA_PER_RDCLK_ALIGN + 55 , 0b1 , any ; # ENA_PER_DQS_ALIGN + 56 , 0b1 , any ; # ENA_PER_READ_CTR + 57:58 , 0b00 , any ; # PER_NEXT_RANK_PAIR + 59 , 0b1 , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR + 59 , 0b0 , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR + 60 , 0b0 , any ; # START_INIT_CAL + 61 , 0b0 , any ; # START_PER_CAL + 62 , 0b0 , any ; # ABORT_ON_ERR_EN + 63 , 0b0 , any ; # ZCAL_UPDATE_MODE } # --------------------------------------------------------------------------------------- @@ -2436,10 +3243,9 @@ scom 0x8001C00B0301143F { # Port 1 # DPHY01_DDRPHY_PC_RELOAD_VALUE0_P0 0x005 0x8000c0050301143f scom 0x800(0,1)C0050301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48 , 0b0 , any ; # PERIODIC_CAL_REQ_EN 49:63 , 0x0001 , any ; # PERIODIC_RELOAD_VALUE0 -# !! problem with right alignment that needs to be 0x0002 instead of 0x0001 -# 49:63 , 0x0002 , any ; # PERIODIC_RELOAD_VALUE0 } # --------------------------------------------------------------------------------------- @@ -2464,23 +3270,23 @@ scom 0x800(0,1)C0050301143F { # _P[0:1] # DPHY01_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0 0x008 0x8000c0080301143f # PHYE.PHYX.SYNTHX.D3SIDEA.PCX.REG08_L2 scom 0x800(0,1)c0080301143f { # _P[0:1] - bits , scom_data , expr ; # must be >= 2... - 48:63 , 0x0000 , (def_is_sim) ; # match dials -# need to fix... -# 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/196605)+1) , any ; # FAST_SIM_PER_CNTR=0 -# 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/765)+1) , any ; # FAST_SIM_PER_CNTR=1 - 48:63 , 0x01D1 , any ; # 464 = 114ms @ 1600MHz + bits , scom_data , expr ; # must be >= 2... +# 0:47 , 0x000000000000 , any ; # reserved +# 48:63 , 0x0000 , (def_is_sim) ; # match dials + 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/196605)+1) , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR=0 + 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/765)+1) , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR=1 +# 48:63 , 0x01D1 , any ; # 464 = 114ms @ 1600MHz } # --------------------------------------------------------------------------------------- # Periodic ZQcal configuration register default=0 # -# DPHY01.DDRPHY_PC_PER_ZCAL_CONFIG_P0 from (alias spydef) # DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0 0x00F 0x8000c00f0301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG15_L2 scom 0x8000C00F0301143F { # Port0 bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # PER_ZCAL_ENA_RANK for ranks [0:7] 48:51 , 0b1000 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] == 1) ; # dimm0 = 1 rank 48:51 , 0b1100 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] == 2) ; # dimm0 = 2 rank @@ -2496,9 +3302,11 @@ scom 0x8000C00F0301143F { # Port0 56:58 , 0b000 , any ; # START_PER_ZCAL 59 , 0b0 , any ; +# 60:63 , 0x0 , any ; reserved } scom 0x8001C00F0301143F { # Port1 bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # PER_ZCAL_ENA_RANK for ranks [0:7] 48:51 , 0b1000 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] == 1) ; # dimm0 = 1 rank 48:51 , 0b1100 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] == 2) ; # dimm0 = 2 rank @@ -2514,6 +3322,7 @@ scom 0x8001C00F0301143F { # Port1 56:58 , 0b000 , any ; # START_PER_ZCAL 59 , 0b0 , any ; +# 60:63 , 0x0 , any ; reserved } # --------------------------------------------------------------------------------------- @@ -2535,51 +3344,66 @@ scom 0x8001C00F0301143F { # Port1 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG09_L2 scom 0x8000c0090301143f { bits , scom_data , expr ; # must be >= 2... -# fix needed from Anuwat to set the attribute value... -# 48:63 , ((ATTR_EFF_ZQCAL_INTERVAL/196605)+1) , (SYS.ATTR_IS_SIMULATION==0) ; # FAST_SIM_PER_CNTR=0 -# 48:63 , ((ATTR_EFF_ZQCAL_INTERVAL/765)+1) , any ; # FAST_SIM_PER_CNTR=1 - 48:63 , 0x002E , any ; # 46 = 11ms @ 1600MHz +# 0:47 , 0x000000000000 , any ; # reserved + 48:63 , ((ATTR_EFF_ZQCAL_INTERVAL/196605)+1) , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR=0 + 48:63 , ((ATTR_EFF_ZQCAL_INTERVAL/765)+1) , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR=1 +# 48:63 , 0x002E , any ; # 46 = 11ms @ 1600MHz } # --------------------------------------------------------------------------------------- -# DPHY01 PC Power Down 1 default=0 +# DPHY01 PC Power Down 1 default=0 !! need to set this? # -# !! need to set this? # This register provides control of the power down modes of the DDR PHY. # # DPHY01_DDRPHY_PC_POWERDOWN_1_P0 0x010 0x8000c0100301143f +# +# asking Ken... - -# PC Rank Group Register -# DDRPHY_PC_RANK_GROUP PC 0x011 -# This register provides control of the rank groups. -# ADDR_MIRROR_RP0_PRI -# ADDR_MIRROR_RP0_SEC -# ADDR_MIRROR_RP1_PRI -# ADDR_MIRROR_RP1_SEC -# ADDR_MIRROR_RP2_PRI -# ADDR_MIRROR_RP2_SEC -# ADDR_MIRROR_RP3_PRI -# ADDR_MIRROR_RP3_SEC -# RANK_GROUPING -# ADDR_MIRROR_A3_A4 -# ADDR_MIRROR_A5_A6 -# ADDR_MIRROR_A7_A8 -# ADDR_MIRROR_A11_A13 -# ADDR_MIRROR_BA0_BA1 -# ADDR_MIRROR_BG0_BG1 - +# --------------------------------------------------------------------------------------- +# PC Rank Group Register no need to set since using RDIMMs +# +# This register provides control of mirrored address bits. Mainly? used for +# UDIMMs? +# +# DPHY01_DDRPHY_PC_RANK_GROUP_P0 0x11 0x8000c0110301143f +# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG17_L2 +#scom 0x8000c0110301143f { +# bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# 48 , 0b0 , any ; # ADDR_MIRROR_RP0_PRI +# 49 , 0b0 , any ; # ADDR_MIRROR_RP0_SEC +# 50 , 0b0 , any ; # ADDR_MIRROR_RP1_PRI +# 51 , 0b0 , any ; # ADDR_MIRROR_RP1_SEC +# 52 , 0b0 , any ; # ADDR_MIRROR_RP2_PRI +# 53 , 0b0 , any ; # ADDR_MIRROR_RP2_SEC +# 54 , 0b0 , any ; # ADDR_MIRROR_RP3_PRI +# 55 , 0b0 , any ; # ADDR_MIRROR_RP3_SEC +# 56:57 , 0b0 , any ; # RANK_GROUPING +# 58 , 0b0 , any ; # ADDR_MIRROR_A3_A4 +# 59 , 0b0 , any ; # ADDR_MIRROR_A5_A6 +# 60 , 0b0 , any ; # ADDR_MIRROR_A7_A8 +# 61 , 0b0 , any ; # ADDR_MIRROR_A11_A13 +# 62 , 0b0 , any ; # ADDR_MIRROR_BA0_BA1 +# 63 , 0b0 , any ; # ADDR_MIRROR_BG0_BG1 +#} +# --------------------------------------------------------------------------------------- # PC Rank Group Extension Register -# DDRPHY_PC_RANK_GROUP_EXT 0x035 -# ADDR_MIRROR_RP0_TER -# ADDR_MIRROR_RP0_QUA -# ADDR_MIRROR_RP1_TER -# ADDR_MIRROR_RP1_QUA -# ADDR_MIRROR_RP2_TER -# ADDR_MIRROR_RP2_QUA -# ADDR_MIRROR_RP3_TER -# ADDR_MIRROR_RP3_QUA - +# +# DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0 0x035 0x8000c0350301143f +# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG53_L2 +#scom 0x8000c0350301143f { +# bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# 48 , 0b0 , any ; # ADDR_MIRROR_RP0_TER +# 49 , 0b0 , any ; # ADDR_MIRROR_RP0_QUA +# 50 , 0b0 , any ; # ADDR_MIRROR_RP1_TER +# 51 , 0b0 , any ; # ADDR_MIRROR_RP1_QUA +# 52 , 0b0 , any ; # ADDR_MIRROR_RP2_TER +# 53 , 0b0 , any ; # ADDR_MIRROR_RP2_QUA +# 54 , 0b0 , any ; # ADDR_MIRROR_RP3_TER +# 55 , 0b0 , any ; # ADDR_MIRROR_RP3_QUA +# 56:63 , 0x00 , any ; # reserved +#} # --------------------------------------------------------------------------------------- # Rank pair 0 configuration register default=0 @@ -2592,11 +3416,14 @@ scom 0x8000c0090301143f { # ATTR_EFF_PRIMARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid # ATTR_EFF_SECONDARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid # -# DPHY01.DDRPHY_PC_RANK_PAIR0_P0 from (alias spydef) # DPHY01_DDRPHY_PC_RANK_PAIR0_P0 0x002 0x8000c0020301143f # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG02_L2 scom 0x8000C0020301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved +# possible way to simplify... +# 48:51 , ((ATTR_EFF_PRIMARY_RANK_GROUP0[0]<<1) | 0x1) , (def_val_prg1_p1) ; # P1_RP1_PRI = 9 +# 48:51 , 0b0000 , any ; # P1_RP1_PRI invalid 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]) , (def_val_prg0_p0) ; # P0_RP0_PRI 48:50 , 0b000 , any ; # P0_RP0_PRI 51 , 0b1 , (def_val_prg0_p0) ; # P0_RP0_PRI_V @@ -2616,9 +3443,10 @@ scom 0x8000C0020301143F { } # -=-=-=-=-=-=-=- PC_RANK_PAIR0 Port 1 -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -# DPHY01.DDRPHY_PC_RANK_PAIR0_P1 from (alias spydef) +# DPHY01.DDRPHY_PC_RANK_PAIR0_P1 scom 0x8001C0020301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP0[1]) , (def_val_prg0_p1) ; # P1_RP0_PRI 48:50 , 0b000 , any ; # P1_RP0_PRI invalid 51 , 0b1 , (def_val_prg0_p1) ; # P1_RP0_PRI_V @@ -2627,8 +3455,6 @@ scom 0x8001C0020301143F { 52:54 , 0b000 , any ; # P1_RP0_SEC invalid 55 , 0b1 , (def_val_srg0_p1) ; # P1_RP0_SEC_V 55 , 0b0 , any ; # P1_RP0_SEC_V invalid -# 56:59 , ((ATTR_EFF_PRIMARY_RANK_GROUP1[1]<<1) | 0x1) , (def_val_prg1_p1) ; # P1_RP1_PRI = 9 -# 56:59 , 0b0000 , any ; # P1_RP1_PRI invalid 56:58 , (ATTR_EFF_PRIMARY_RANK_GROUP1[1]) , (def_val_prg1_p1) ; # P1_RP1_PRI 56:58 , 0b000 , any ; # P1_RP1_PRI invalid 59 , 0b1 , (def_val_prg1_p1) ; # P1_RP1_PRI_V @@ -2648,9 +3474,10 @@ scom 0x8001C0020301143F { # ATTR_EFF_PRIMARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid # ATTR_EFF_SECONDARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid # -# DPHY01.DDRPHY_PC_RANK_PAIR1_P0 from (alias spydef) +# DPHY01.DDRPHY_PC_RANK_PAIR1_P0 scom 0x8000C0030301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]) , (def_val_prg2_p0) ; # P0_RP2_PRI 48:50 , 0b000 , any ; # P0_RP2_PRI invalid 51 , 0b1 , (def_val_prg2_p0) ; # P0_RP2_PRI_V @@ -2670,9 +3497,10 @@ scom 0x8000C0030301143F { } # -=-=-=-=-=-=-=- PC_RANK_PAIR1 Port 1 -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -# DPHY01.DDRPHY_PC_RANK_PAIR1_P1 from (alias spydef) +# DPHY01.DDRPHY_PC_RANK_PAIR1_P1 scom 0x8001C0030301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP2[1]) , (def_val_prg2_p1) ; # P1_RP2_PRI 48:50 , 0b000 , any ; # P1_RP2_PRI invalid 51 , 0b1 , (def_val_prg2_p1) ; # P1_RP2_PRI_V @@ -2704,6 +3532,7 @@ scom 0x8001C0030301143F { # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG48_L2 scom 0x8000c0300301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP0[0]) , (def_val_trg0_p0) ; # P0_RP0_TER 48:50 , 0b000 , any ; # P0_RP0_TER invalid 51 , 0b1 , (def_val_trg0_p0) ; # P0_RP0_TER_V @@ -2726,6 +3555,7 @@ scom 0x8000c0300301143f { # DPHY01.DDRPHY_PC_RANK_PAIR2_P1 scom 0x8001c0300301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP0[1]) , (def_val_trg0_p1) ; # P1_RP0_TER 48:50 , 0b000 , any ; # P1_RP0_TER invalid 51 , 0b1 , (def_val_trg0_p1) ; # P1_RP0_TER_V @@ -2757,6 +3587,7 @@ scom 0x8001c0300301143f { # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG49_L2 scom 0x8000c0310301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP2[0]) , (def_val_trg2_p0) ; # P0_RP2_TER 48:50 , 0b000 , any ; # P0_RP2_TER invalid 51 , 0b1 , (def_val_trg2_p0) ; # P0_RP2_TER_V @@ -2779,6 +3610,7 @@ scom 0x8000c0310301143f { # DPHY01.DDRPHY_PC_RANK_PAIR3_P1 scom 0x8001c0310301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP2[1]) , (def_val_trg2_p1) ; # P1_RP2_TER 48:50 , 0b000 , any ; # P1_RP2_TER invalid 51 , 0b1 , (def_val_trg2_p1) ; # P1_RP2_TER_V @@ -2800,18 +3632,31 @@ scom 0x8001c0310301143f { # --------------------------------------------------------------------------------------- # Read Control Configuration 0 default=0x0002 # -# DPHY01.DDRPHY_RC_CONFIG0_P0 from (alias spydef) -# DPHY01.DDRPHY_RC_CONFIG0_P1 from (alias spydef) +# DPHY01.DDRPHY_RC_CONFIG0_P0 +# DPHY01.DDRPHY_RC_CONFIG0_P1 +# +# num of tCK cycles = 300 + [(PER_REPEAT_COUNT + 1) * 600] # # DPHY01_DDRPHY_RC_CONFIG0_P0 0x000 0x8000c8000301143f # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG0_L2 scom 0x800(0,1)C8000301143F { # _P[0:1] bits , scom_data , expr ; - # min GPO=5 +# 0:47 , 0x000000000000, any ; # reserved + # + # System_Delay = ( ( (ADR_DELAY - 64) + + # {wire delay from the PHY memory clock output to the DRAM module converted to units of 1/128th of a MEMINTCLKO clock cycle} + + # {delay of DQS at the memory module pin relative to memory clock at the memory module pin introduced by the memory module + # (that is, tDQSCK) converted to units of 1/128th of a MEMINTCLKO clock cycle} + + # {wire delay from the DRAM DQS output to the PHY converted to units of 1/128th of a MEMINTCLKO clock cycle}) / 128) + + # {number of pipeline stages in the addr/cmd path} + + # {number of pipeline stages in the read data path} + # + # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN + # max GPO = 11 if in 2:1, 13 if in 4:1 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), 2:1 max=11, 4:1 max=13 - 52 , 0b0 , any ; # ADVANCE_RD_VALID + 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen 53 , 0b0 , any ; # ERS_MODE, reserved - 54:56 , 0b000 , any ; # PER_REPEAT_COUNT + 54:56 , 0b000 , any ; # PER_REPEAT_COUNT, (value+1)=num bits per peridic cal 57 , 0b0 , any ; # SINGLE_BIT_MPR_RP0 58 , 0b0 , any ; # SINGLE_BIT_MPR_RP1 59 , 0b0 , any ; # SINGLE_BIT_MPR_RP2 @@ -2825,13 +3670,14 @@ scom 0x800(0,1)C8000301143F { # _P[0:1] # --------------------------------------------------------------------------------------- # Read Control Configuration 1 default=0x0000 # -# DPHY01.DDRPHY_RC_CONFIG1_P0 from (alias spydef) -# DPHY01.DDRPHY_RC_CONFIG1_P1 from (alias spydef) +# DPHY01.DDRPHY_RC_CONFIG1_P0 +# DPHY01.DDRPHY_RC_CONFIG1_P1 # # DPHY01_DDRPHY_RC_CONFIG1_P0 0x001 0x8000c8010301143f # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.ITERATION_COUNT_L2 scom 0x800(0,1)C8010301143F { # _P[0:1] bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved 48:61 , 0b00000000000000 ; # OUTER_LOOP_CNT # 62:63 , 0b00 ; # reserved } @@ -2839,14 +3685,15 @@ scom 0x800(0,1)C8010301143F { # _P[0:1] # --------------------------------------------------------------------------------------- # Read Control Configuration 2 default=0x4008 # -# DPHY01.DDRPHY_RC_CONFIG2_P0 from (alias spydef) -# DPHY01.DDRPHY_RC_CONFIG2_P1 from (alias spydef) +# DPHY01.DDRPHY_RC_CONFIG2_P0 +# DPHY01.DDRPHY_RC_CONFIG2_P1 # # DPHY01_DDRPHY_RC_CONFIG2_P0 0x002 0x8000c8020301143f # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG2_L2 scom 0x800(0,1)C8020301143F { # _P[0:1] bits , scom_data , expr ; - 48:52 , 0b00000 , (def_is_sim) ; # CONSEQ_PASS sim value +# 0:47 , 0x000000000000, any ; # reserved +# 48:52 , 0b00000 , (def_is_sim) ; # CONSEQ_PASS sim value 48:52 , 0b00110 , (def_is_bl8) ; # CONSEQ_PASS 6 min for BL8 48:52 , 0b01100 , any ; # CONSEQ_PASS 12 min for BL4, or OTF # 53:56 , 0b0000 , any ; # reserved @@ -2860,24 +3707,24 @@ scom 0x800(0,1)C8020301143F { # _P[0:1] # --------------------------------------------------------------------------------------- # Read Control Configuration 3 default=0x0800 # -# DPHY01.DDRPHY_RC_CONFIG3_P0 from (alias spydef) -# DPHY01.DDRPHY_RC_CONFIG3_P1 from (alias spydef) +# DPHY01.DDRPHY_RC_CONFIG3_P0 +# DPHY01.DDRPHY_RC_CONFIG3_P1 # # DPHY01_DDRPHY_RC_CONFIG3_P0 0x007 0x8000c8070301143f # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG3_L2(0:6),PHYW.PHYX.SYNTHX.D3SIDEA.RCX.DQSDQ_ENUM_COUNT_L2 scom 0x800(0,1)C8070301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # FINE_CAL_STEP_SIZE (000=1/128, 001=1/64, 010=3/128, 011=1/32...) 48:50 , 0b000 , any ; # 1/128 # COARSE_CAL_STEP_SIZE same as above but 8-16 reserved, but when DIGITAL_EYE_EN=1 # in DFT_DIG_EYE register, 51:52 reserved, 53=DIGEYE_16_NOT_1, 54= DIGEYE_REFRESH - #51:54 , 0b0100 , (def_is_sim) ; # COARSE_CAL_STEP_SIZE = 4 = 5/128 # old 5/18 - #51:54 , 0b1100 , any ; # COARSE_CAL_STEP_SIZE # old 5/18 - 51:54 , 0b1010 , (def_is_sim) ; # COARSE_CAL_STEP_SIZE - 51:54 , 0b0000 , any ; # COARSE_CAL_STEP_SIZE + 51:54 , 0b1010 , (def_is_sim) ; # COARSE_CAL_STEP_SIZE # old=4=5/128 (5/18) + 51:54 , 0b0000 , any ; # COARSE_CAL_STEP_SIZE = 1/128 55:56 , 0b00 , any ; # DQ_SEL_QUAD 57:59 , 0b000 , any ; # DQ_SEL_LANE +# 60:63 , 0b0000 , any ; # reserved } # --------------------------------------------------------------------------------------- @@ -2889,19 +3736,23 @@ scom 0x800(0,1)C8070301143F { # _P[0:1] # --------------------------------------------------------------------------------------- # SEQ Configuration 0 Register default=0 !! need to review settings # -# DPHY01.DDRPHY_SEQ_CONFIG0_P0 from (alias spydef) -# DPHY01.DDRPHY_SEQ_CONFIG0_P1 from (alias spydef) +# DPHY01.DDRPHY_SEQ_CONFIG0_P0 +# DPHY01.DDRPHY_SEQ_CONFIG0_P1 # # DPHY01_DDRPHY_SEQ_CONFIG0_P0 CTL 0x002 0x8000c4020301143f # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MPR_PATTERN_DATA_L2 scom 0x800(0,1)C4020301143F { # _P[0:1] bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved 48 , 0b0 ; # MPR_PATTERN_BIT 49 , 0b0 ; # TWO_CYCLE_ADDR_EN (must be set to 0), need 1 in sim ? 2N 50:53 , 0b0000 ; # MR_MASK_EN (mode register[0:3] mask during calibration) - 54 , 0b0 ; # PARITY_DLY (only for DDR4, DDR3 don't care) + 54 , 0b0 ; # DELAYED_PARITY (only for DDR4, DDR3 don't care) 55 , 0b0 ; # LRDIMM_CONTEXT -# 56:63 , 0b00000000 ; # reserved + 56 , 0b0 ; # FORCE_RESERVED + 57 , 0b0 ; # HALT_ROTATION + 58 , 0b0 ; # FORCE_MPR +# 59:63 , 0b00000 ; # reserved } # --------------------------------------------------------------------------------------- @@ -2962,30 +3813,26 @@ scom 0x800(0,1)C4020301143F { # _P[0:1] # 2259 = .8853ns 10.624 ns 14.16 ns 17 21.25 ns* # 3200 0.625ns # -# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 from (alias spydef) # [01:23] [0:2] [0:1] # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 CTL 0x012 0x8000c4120301143f # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM0_L2 scom 0x800(0,1)C4120301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # TMOD_CYCLES, DDR3=max(12nCK, 15ns), DDR4=max(24nCK, 15ns) -# 48:51 , 0x7 , (def_is_sim) ; # match dials - 48:51 , 0x4 , ((CEN.ATTR_MSS_FREQ <= 2133) && (def_is_ddr3)) ; # DDR3 && < 2133, 2^4 = 16clks - 48:51 , 0x5 , ((CEN.ATTR_MSS_FREQ > 2133) && (def_is_ddr3)) ; # DDR3 && > 2133, 2^5 = 32clks - 48:51 , 0x5 , ((CEN.ATTR_MSS_FREQ < 3200) && (def_is_ddr4)) ; # DDR4 && < 3200, 2^5 = 32clks + 48:51 , 0x4 , ((CEN.ATTR_MSS_FREQ <= 2133) && (def_is_ddr3)) ; # DDR3 && < 2133, 2^4 = 16clks + 48:51 , 0x5 , ((CEN.ATTR_MSS_FREQ > 2133) && (def_is_ddr3)) ; # DDR3 && > 2133, 2^5 = 32clks + 48:51 , 0x5 , ((CEN.ATTR_MSS_FREQ < 3200) && (def_is_ddr4)) ; # DDR4 && < 3200, 2^5 = 32clks # TRCD_CYCLES -# 52:55 , 0x7 , (def_is_sim) ; # match dials 52:55 , 0x4 , ((ATTR_EFF_DRAM_TRCD > 8) && (ATTR_EFF_DRAM_TRCD <= 16)) ; # 2^4 = 16 clks 52:55 , 0x3 , (ATTR_EFF_DRAM_TRCD <= 8) ; # 2^3 = 8 clks 52:55 , 0x5 , (ATTR_EFF_DRAM_TRCD > 16) ; # 2^5 = 32 clks # TRP_CYCLES -# 56:59 , 0x7 , (def_is_sim) ; # match dials 56:59 , 0x3 , (ATTR_EFF_DRAM_TRP < 8) ; # 2^3 = 8 clks 56:59 , 0x4 , ((ATTR_EFF_DRAM_TRP > 8) && (ATTR_EFF_DRAM_TRP <= 16)) ; # 2^4 = 16 clks 56:59 , 0x5 , (ATTR_EFF_DRAM_TRP > 16) ; # 2^5 = 32 clks # TRFC_CYCLES, based on Gb density (512=90ns 1Gb=110ns 2Gb=160ns 4Gb=300ns 8Gb=350ns) # ATTR_EFF_DRAM_TRFC in clocks = tRFC / clock -# 60:63 , 0x7 , (def_is_sim) ; # match dials 60:63 , 0x6 , ((ATTR_EFF_DRAM_TRFC <= 64) && (ATTR_EFF_DRAM_TRFC > 32)) ; # 2^6 = 64 clks 60:63 , 0x7 , ((ATTR_EFF_DRAM_TRFC <= 128) && (ATTR_EFF_DRAM_TRFC > 64)) ; # 2^7 = 128 clks 60:63 , 0x8 , ((ATTR_EFF_DRAM_TRFC <= 256) && (ATTR_EFF_DRAM_TRFC > 128)) ; # 2^8 = 256 clks @@ -2998,27 +3845,23 @@ scom 0x800(0,1)C4120301143F { # _P[0:1] # Memory Timing Parameters to be used during calibration. Each nibble is used as # exponent of 2, to calculate # of clock cycles. Ex: TZQCS_CYCLES=6, 2^6 clocks # -# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 from (alias spydef) # [01:23] [0:2] [0:1] # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 CTL 0x013 0x8000c4130301143f # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM1_L2 scom 0x800(0,1)C4130301143F { # _P[0:1] - bits , scom_data , expr ; + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # TZQINIT_CYCLES max(tZQINIT,tZQOPER) DDR3=max(512nCK, 640ns) DDR4=1024nCK -# 48:51 , 0x7 , (def_is_sim) ; # match dials 48:51 , 0x9 , ((def_is_ddr3) && (CEN.ATTR_MSS_FREQ <= 1600)) ; # DDR3 & freq <= 1600, 512 clks 48:51 , 0xA , ((def_is_ddr4) || (CEN.ATTR_MSS_FREQ > 1600)) ; # DDR4 || freq > 1600, 1024 clks # TZQCS_CYCLES DDR3=max(64nCK, 80ns) DDR4=128nCK -# 52:55 , 0x7 , (def_is_sim) ; # match dials 52:55 , 0x6 , ((def_is_ddr3) && (CEN.ATTR_MSS_FREQ <= 1600)) ; # DDR3 & freq <= 1600, 64 clks 52:55 , 0xA , ((def_is_ddr4) || (CEN.ATTR_MSS_FREQ > 1600)) ; # DDR4 || freq > 1600, 128 clks +# *Note: max values system dependent # TWLDQSEN_CYCLES DDR3/4=min(25nCK)* -# 56:59 , 0x7 , (def_is_sim) ; # match dials - 56:59 , 0x5 , any ; # 2^5 = 32 clks + 56:59 , 0x5 , any ; # 2^5 = 32 clks # TWLMRD_CYCLES DDR3/4=min(40nCK)* -# 60:63 , 0x7 , (def_is_sim) ; # match dials - 60:63 , 0x6 , any ; # 2^6 = 64 clks -# *Note: max values system dependent + 60:63 , 0x6 , any ; # 2^6 = 64 clks } # --------------------------------------------------------------------------------------- @@ -3027,16 +3870,15 @@ scom 0x800(0,1)C4130301143F { # _P[0:1] # Memory Timing Parameters to be used during calibration. Each nibble is used as # exponent of 2, to calculate # of clock cycles. Ex: TRCS_CYCLES=0, 2^0 clocks # -# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 from (alias spydef) # [01:23] [0:2] [0:1] # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 CTL 0x014 0x8000c4140301143f # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM2_L2 -# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 from (alias spydef) # # TODTLON_OFF_CYCLES DDR3=CWL+AL-2 DDR4 if 2tCK, CWL+AL-3 # define def_tODTL_DDR3_AL0 = def_tODTL_DDR3 - ATTR_EFF_DRAM_CL ; # scom 0x800(0,1)C4140301143F { # _P[0:1] # bits , scom_data , ATTR_EFF_DRAM_GEN , ATTR_EFF_DRAM_AL , expr ; +# 0:47 , 0x000000000000, any , any , any ; # reserved # #--------------- DDR3 ------------------------------------------------------------------------- # 48:51 , 0x3 , 1 , 0 , (def_tODTL_DDR3_AL0 <= 8) ; # 8 clks # 48:51 , 0x4 , 1 , 0 , ((def_tODTL_DDR3_AL0 <= 16) && (def_tODTL_DDR3_AL0 > 8)) ; # 16 clks @@ -3057,20 +3899,19 @@ scom 0x800(0,1)C4130301143F { # _P[0:1] # 48:51 , 0x6 , 2 , any , ((def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32)) ; # 64 clks # 48:51 , 0x0 , any , any , any ; # 0 clks # # TRC_CYCLES -# 52:55 , 0x7 , (def_is_sim) ; # match dials # 52:55 , 0x7 , ((ATTR_EFF_DRAM_TRC > 64) && (ATTR_EFF_DRAM_TRC <= 128)) ; # 2^7 = 128 clks # 52:55 , 0x6 , ((ATTR_EFF_DRAM_TRC > 32) && (ATTR_EFF_DRAM_TRC <= 64)) ; # 2^6 = 64 clks # 52:55 , 0x5 , ((ATTR_EFF_DRAM_TRC > 16) && (ATTR_EFF_DRAM_TRC <= 32)) ; # 2^5 = 32 clks # 52:55 , 0x4 , ((ATTR_EFF_DRAM_TRC > 8) && (ATTR_EFF_DRAM_TRC <= 16)) ; # 2^4 = 16 clks # 52:55 , 0x3 , (ATTR_EFF_DRAM_TRC <= 8) ; # 2^3 = 8 clks # # TMRSC_CYCLES for RLDRAMs, set to 0 for everything else -# 56:59 , 0x7 , (def_is_sim) ; # match dials # 56:59 , 0x0 , any ; # # 60:63 , 0x0 , any ; # reserved # } scom 0x800(0,1)C4140301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved # TODTLON_OFF_CYCLES DDR3=CWL+AL-2 DDR4 if 2tCK, CWL+AL-3 #--------------- DDR3 ------------------------------------------------------------------------- 48:51 , 0x3 , ((def_is_ddr3) && (def_tODTL_DDR3 <= 8)) ; # 8 clks @@ -3084,19 +3925,19 @@ scom 0x800(0,1)C4140301143F { # _P[0:1] 48:51 , 0x6 , ((def_is_ddr4) && (def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32)) ; # 64 clks 48:51 , 0x0 , any ; # 0 clks # TRC_CYCLES - 52:55 , 0x7 , (def_is_sim) ; # match dials +# 52:55 , 0x7 , (def_is_sim) ; # match dials 52:55 , 0x7 , ((ATTR_EFF_DRAM_TRC > 64) && (ATTR_EFF_DRAM_TRC <= 128)) ; # 2^7 = 128 clks 52:55 , 0x6 , ((ATTR_EFF_DRAM_TRC > 32) && (ATTR_EFF_DRAM_TRC <= 64)) ; # 2^6 = 64 clks 52:55 , 0x5 , ((ATTR_EFF_DRAM_TRC > 16) && (ATTR_EFF_DRAM_TRC <= 32)) ; # 2^5 = 32 clks 52:55 , 0x4 , ((ATTR_EFF_DRAM_TRC > 8) && (ATTR_EFF_DRAM_TRC <= 16)) ; # 2^4 = 16 clks 52:55 , 0x3 , (ATTR_EFF_DRAM_TRC <= 8) ; # 2^3 = 8 clks # TMRSC_CYCLES for RLDRAMs, set to 0 for everything else - 56:59 , 0x7 , (def_is_sim) ; # match dials +# 56:59 , 0x7 , (def_is_sim) ; # match dials 56:59 , 0x0 , any ; # 60:63 , 0x0 , any ; # reserved } # --------------------------------------------------------------------------------------- -# SEQ Low Power Termination Address default=0xFFFF !! need to set this? +# SEQ Low Power Termination Address default=0xFFFF # # bit positions and mapping of the Address/BA/BG pins in DDR3/DDR4 of the low power # termination address{2-4} @@ -3118,6 +3959,7 @@ scom 0x800(0,1)C4140301143F { # _P[0:1] #DPHY01_DDRPHY_SEQ_LPT_ADDR2_P0 0x017 0x8000c4170301143f #scom 0x8000c4170301143f { # bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved # 48:63 , 0xFFFF ; # LPT_ADDR2 #} @@ -3130,15 +3972,22 @@ scom 0x800(0,1)C4140301143F { # _P[0:1] # DPHY01_DDRPHY_WC_CONFIG0_P0 0x000 0x8000cc000301143f # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG0_L2 scom 0x800(0,1)CC000301143F { # _P[0:1] - bits , scom_data , expr ; + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved +# !! need to review # = 12 + max(tWLDQSEN-tMOD,tWLO+tWLOE) + (longest DQS wire delay in CKs) + (longest DQ wire delay in CKs) + 48:55 , 0x10 , any ; # TWLO_TWLOE = 16 (same as DD0) # @ 1600, = 12 + max(13,3) + ldqs + ldq = 25 + ldqs + ldq - 48:55 , 0x10 , (def_is_sim) ; # TWLO_TWLOE = 16 - 48:55 , 0x1B , any ; # TWLO_TWLOE = 27 - #48:55 , (25+ldqs+ldq), < 1866 ; # TWLO_TWLOE - 56 , 0b1 , any ; # WL_ONE_DQS_PULSE = enable - 57:62 , 0b000000 , any ; # FW_WR_RD - 63 , 0b0 , any ; # CUSTOM_INIT_WRITE + #48:55 , 0x1B , any ; # TWLO_TWLOE = 27 + #48:55 , (25+ldqs+ldq) , (CEN.ATTR_MSS_FREQ > 1460) ; # TWLO_TWLOE (> 1333) + 56 , 0b1 , any ; # WL_ONE_DQS_PULSE = enable + # FW_WR_RD = max(tWTR+8,AL+tRTP), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0 + 57:62 , 0b000000 , (def_is_sim) ; + 57:62 , 0b010001 , any ; # same as DD0, right aligned here, 17d + 57:62 , (def_TWTR_PLUS_8) , (def_TWTR_PLUS_8 >= def_TRTP_PLUS_AL) ; # TWTR + 8 >= TRTP + AL + 57:62 , (def_TRTP_PLUS_AL) , (def_TWTR_PLUS_8 < def_TRTP_PLUS_AL) ; # TWTR + 8 < TRTP + AL + + 63 , 0b0 , any ; # CUSTOM_INIT_WRITE } # --------------------------------------------------------------------------------------- # Write control logic configuration 1 default=0x2350 addr=0xCC01 @@ -3147,6 +3996,8 @@ scom 0x800(0,1)CC000301143F { # _P[0:1] # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG1_L2 scom 0x800(0,1)CC010301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# !! need to review 48:51 , 0b1100 , (def_is_sim) ; # BIG_STEP = 12 (changed from default for SIM) 48:51 , 0b0010 , any ; # BIG_STEP = 2 (default) 52:54 , 0b001 , any ; # SMALL_STEP = 1 (!! recommend setting to 0) @@ -3157,12 +4008,11 @@ scom 0x800(0,1)CC010301143F { # _P[0:1] # --------------------------------------------------------------------------------------- # Write control logic configuration 2 default=0x5440 # -# DPHY01.DDRPHY_WC_CONFIG2_P0 from (alias spydef) -# # DPHY01_DDRPHY_WC_CONFIG2_P0 0x002 0x8000cc020301143f # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG2_L2 scom 0x800(0,1)CC020301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved 48:51 , 0x3 , (def_is_sim) ; # NUM_VALID_SAMPLES = 3 (changed from defaults) 48:51 , 0x5 , any ; # NUM_VALID_SAMPLES = 5 (defaults) @@ -3170,6 +4020,13 @@ scom 0x800(0,1)CC020301143F { # _P[0:1] 52:57 , (def_TWTR_PLUS_8) , (def_TWTR_PLUS_8 >= def_TRTP_PLUS_AL) ; # TWTR + 8 >= TRTP + AL 52:57 , (def_TRTP_PLUS_AL) , (def_TWTR_PLUS_8 < def_TRTP_PLUS_AL) ; # TWTR + 8 < TRTP + AL +# RL=CL+AL, WL=CWL+AL !! Need to fix +# = CL + 2tCK + tCCD/x x=1 if +# Read to write = RL + tCCD + 2tCK - WL (in DDR3 JEDEC for Read BL8 to Write BL8) +# Read to write = RL + tCCD/2 + 2tCK - WL (in DDR3 JEDEC for Read BC4 to Write BC4/BL8 OTF) +# 52:57 , def_fw_rd_wr, , (def_TWTR_PLUS_8 < def_TRTP_PLUS_AL) ; # TWTR + 8 < TRTP + AL + + # 58:62 , 0b00000 , any ; # reserved # DP18_WR_DELAY_VALUE_{0-23}_RP{0-3}_REG are reset to 0 at the start of WL cal for rank pair 0 when '1' @@ -3179,14 +4036,14 @@ scom 0x800(0,1)CC020301143F { # _P[0:1] # --------------------------------------------------------------------------------------- # Write control logic configuration 3 default=0x01F8 # -# DPHY01.DDRPHY_WC_CONFIG3_P0 from (alias spydef) -# # DPHY01_DDRPHY_WC_CONFIG3_P0 0x005 0x8000cc050301143f # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG3_L2 scom 0x800(0,1)CC050301143F { # _P[0:1] bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48 , 0b1 , (def_is_ddr4) ; # if DDR4, drive DQ pins in DATA_BIT_ENABLE1 48 , 0b0 , (def_not_ddr4) ; # if not DDR4, set to 0 +# !! need to review # MRS_CMD_DQ_ON determines the WL_per_DRAM_addr time. # WL_per_DRAM_addr = 10 + MRS_CMD_DQ_ON in 2:1 mode # WL_per_DRAM_addr = 18 + 2 * MRS_CMD_DQ_ON in 4:1 mode @@ -3197,7 +4054,7 @@ scom 0x800(0,1)CC050301143F { # _P[0:1] } # --------------------------------------------------------------------------------------- -# DP18 Data Bit Direction 0 defaults to 0's !! need to set this? +# DP18 Data Bit Direction 0 defaults to 0's no longer need to set this. # # 1 indicates output only # @@ -3209,20 +4066,17 @@ scom 0x800(0,1)CC050301143F { # _P[0:1] # # '1'b indicates DP18 bit is an output and continously drives out a signal # -# DPHY01.DDRPHY_DP18_DATA_BIT_DIR1_P0_0 from (alias spydef) # DPHY01_DDRPHY_DP18_DATA_BIT_DIR1_P0_0 0x003 0x800000030301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DIR1_L2 #scom 0x800(0,1)(00,04,08,0C,10)030301143f { # DIR1_P[0:1]_[0:4] scom 0x800(0,1)3C030301143f { # DIR1_P[0:1]_[0:4] via broadcast bits , scom_data , expr ; - 48:55 , 0b00000000 , any ; # DATA_BIT_DIR_16_23 +# 0:47 , 0x000000000000, any ; # reserved +# 48:54 , 0b0000000 , any ; # reserved... used to be DATA_BIT_DIR_16_23 + 55 , 0b0 , any ; # ATEST_MUX_CTL_EN 56 , 0b0 , any ; # WL_ADVANCE_DISABLE 57 , 0b0 , any ; # DISABLE_PING_PONG -# !recent -# 58 , 0b0 , (def_is_sim) ; # DELAY_PING_PONG_HALF, to match dials 58 , 0b1 , any ; # DELAY_PING_PONG_HALF, must be 1 from definition -# !recent -# 59 , 0b0 , (def_is_sim) ; # ADVANCE_PING_PONG. to match dials 59 , 0b1 , any ; # ADVANCE_PING_PONG. must be 1 from definition 60:63 , 0b0000 , any ; # ATEST_MUX_CTL[0:3] } @@ -3241,69 +4095,78 @@ scom 0x800(0,1)3C030301143f { # DIR1_P[0:1]_[0:4] via broadcast # P2_4{56:63}, P3_1{56:63} = 0xFF if spares enabled else 0x00 # all others (P2_[0:3], P3_0, P3_[2:4]) = 0xFFFF # -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0 0x800000000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2 0x800008000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3 0x80000C000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0 0x800100000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3 0x80010C000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4 0x800110000301143f -# # [01:23] [0:1]_[0:1]_[0:4] # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0 0x000 0x800000000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2 0x800008000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3 0x80000C000301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_ENABLE0_L2 -# ENABLE0_(P0_0, P0_2, P0_3, P2_0, P2_2, P2_3) +# +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0 0x800000000301143f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2 0x800008000301143f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3 0x80000C000301143f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_0 0x800000000301183f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_2 0x800008000301183f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_3 0x80000C000301183f scom 0x800(000,008,00C)000301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:63 , 0xFFFF , (def_valid_p0) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0x0000 , any ; } + # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0 0x800100000301143f # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3 0x80010C000301143f # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4 0x800110000301143f -# ENABLE0_(P1_0, P1_3, P1_4, P3_0, P3_3, P3_4) +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_0 0x800100000301183f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_3 0x80010C000301183f +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_4 0x800110000301183f scom 0x800(100,10C,110)000301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:63 , 0xFFFF , (def_valid_p1) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0x0000 , any ; } # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4 0x800010000301143f -scom 0x800(010)000301143f { +scom 0x800010000301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p0)) ; # enable DATA_BIT_ENABLE_0_15 -# ENABLE0_(P2_4) +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_4 0x800010000301183f 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p0) && (def_has_spare)) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0xFF00 , ((def_is_mba23) && (def_valid_p0) && (def_no_spare)) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0x0000 , any ; } + # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1 0x800104000301143f -scom 0x800(104)000301143f { +scom 0x800104000301143f { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p1)) ; # enable DATA_BIT_ENABLE_0_15 -# ENABLE0_(P3_1) +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_1 0x800104000301183f 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p1) && (def_has_spare)) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0xFF00 , ((def_is_mba23) && (def_valid_p1) && (def_no_spare)) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0x0000 , any ; } -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_1 0x800004000301183f -scom 0x800(004)000301143f { +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1 0x800004000301143f +scom 0x800004000301143f { bits , scom_data , expr ; - 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p0)) ; # enable DATA_BIT_ENABLE_0_15 -# ENABLE0_(P0_1) +# 0:47 , 0x000000000000, any ; # reserved 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p0) && (def_has_spare)) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0xFF00 , ((def_is_mba01) && (def_valid_p0) && (def_no_spare)) ; # enable DATA_BIT_ENABLE_0_15 +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_1 0x800004000301183f + 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p0)) ; # enable DATA_BIT_ENABLE_0_15 48:63 , 0x0000 , any ; } -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_2 0x800108000301183f -scom 0x800(108)000301143f { # DATA_BIT_ENABLE_0_15 + +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2 0x800108000301143f +scom 0x800108000301143f { bits , scom_data , expr ; # spare = 8_15 - 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p1)) ; # P3_2 -# ENABLE0_(P1_2) +# 0:47 , 0x000000000000, any ; # reserved 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p1) && (def_has_spare)) ; # P1_2, enable spare if CDIMM 48:63 , 0xFF00 , ((def_is_mba01) && (def_valid_p1) && (def_no_spare)) ; # P1_2, disable spare +# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_2 0x800108000301183f + 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p1)) ; # P3_2 + 48:63 , 0x0000 , any ; } # --------------------------------------------------------------------------------------- @@ -3316,6 +4179,7 @@ scom 0x800(108)000301143f { # DATA_BIT_ENABLE_0_15 #scom 0x800(0,1)(00,04,08,0C,10)010301143f { # ENABLE1_P[0:1]_[0:4] # scom 0x800(0,1)3C010301143f { # ENABLE0_P[0:1]_[0:4] via broadcast # bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved # 48:55 , 0b00000000 ; # data_bit_enable_16_23 # 56 , 0b0 ; # DFT_FORCE_OUTPUTS # 57 , 0b0 ; # DFT_PRBS7_GEN_EN @@ -3330,152 +4194,12 @@ scom 0x800(108)000301143f { # DATA_BIT_ENABLE_0_15 #--------------------------------------------------------------------------- # DP18 Data Bit Disable 0 default=0 per Rank Group/Pair # -# This register is used to disable each of the 24 pins on the DP18. During calibration -# operations, the hardware sets the bit in this register which corresponds to a pin on the -# DP18 which failed a calibration step. This register indicates which DQ pins on the DP18 -# failed a calibration step. This register does not indicate which calibration step failed. -# -# !! does the reset clear these 2 registers? does the initfile need to set these? -# ATTR_MSS_BAD_BIT_MASK[port][dimm][rank][byte] -# PHY logic registers only care about bits on a rank pair/port, so dimm will not be needed. -# -# get rank pair via ATTR_EFF_PRIMARY_RANK_GROUP0[0],sec,ter,qua then 'or' the byte together to form -# the value needed for register -# -# NOTE: No need to disable spare dram bits since it should not be enabled. -# port P0_1, P0_4, -# 56:63 , 0xFF , ((def_no_spare) && (def_is_mba01)) ; # disable spare bits -# -#define def_bb_p0_rp0_d = ATTR_EFF_PRIMARY_RANK_GROUP0[0] >> 2; -#define def_bb_p0_rp0_r = ATTR_EFF_PRIMARY_RANK_GROUP0[0] & 0x03; -#define SYS.ATTR_SCRATCH_UINT8_1 = ATTR_EFF_PRIMARY_RANK_GROUP0[0] >> 2; -#define SYS.ATTR_SCRATCH_UINT8_2 = ATTR_EFF_PRIMARY_RANK_GROUP0[0] & 0x03; -# define def_bb_p0_rp1_d = ATTR_EFF_PRIMARY_RANK_GROUP1[0] >> 2; -# define def_bb_p0_rp1_r = ATTR_EFF_PRIMARY_RANK_GROUP1[0] & 0x03; -# define def_bb_p0_rp2_d = ATTR_EFF_PRIMARY_RANK_GROUP2[0] >> 2; -# define def_bb_p0_rp2_r = ATTR_EFF_PRIMARY_RANK_GROUP2[0] & 0x03; -# define def_bb_p0_rp3_d = ATTR_EFF_PRIMARY_RANK_GROUP3[0] >> 2; -# define def_bb_p0_rp3_r = ATTR_EFF_PRIMARY_RANK_GROUP3[0] & 0x03; +# Procedure function to set this register, pulling data from the SPD. +# 1 = disable dq bit # # DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0 0x07C 0x8000007c0301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_L2 -scom 0x8000007C0301143f { # DATA_BIT_DISABLE0_RP0_P0_0 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 -# 48:55 , (ATTR_MSS_BAD_BIT_MASK[0][(ATTR_EFF_PRIMARY_RANK_GROUP0[0] >> 2)][(ATTR_EFF_PRIMARY_RANK_GROUP0[0] & 0x03)][0] , any ; -# 48:55 , (ATTR_MSS_BAD_BIT_MASK[0][def_bb_p0_rp0_d][def_bb_p0_rp0_r][0]) , any ; # expr for byte0 -# 48:55 , 0x55 , (ATTR_MSS_BAD_BIT_MASK[0][SYS.ATTR_SCRATCH_UINT8_1][0][0] == 0x04) -# 48:55 , 0x55 , (ATTR_EFF_DIMM_SIZE[0][SYS.ATTR_SCRATCH_UINT8_1] == 0x00); - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 - #56:63 , (ATTR_MSS_BAD_BIT_MASK[0][def_bb_p0_rp0_d][def_bb_p0_rp0_r][1]) , any ; # expr for byte1 -} -scom 0x8000047C0301143f { # DATA_BIT_DISABLE0_RP0_P0_1 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 -} -scom 0x8000087C0301143f { # DATA_BIT_DISABLE0_RP0_P0_2 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 -} -scom 0x80000C7C0301143f { # DATA_BIT_DISABLE0_RP0_P0_3 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 -} -scom 0x8000107C0301143f { # DATA_BIT_DISABLE0_RP0_P0_4 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255) ; # invalid rank pair0 -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0 0x17C 0x8000017c0301143f -scom 0x8000017C0301143f { # DATA_BIT_DISABLE0_RP1_P0_0 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 -} -scom 0x8000057C0301143f { # DATA_BIT_DISABLE0_RP1_P0_1 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 -} -scom 0x8000097C0301143f { # DATA_BIT_DISABLE0_RP1_P0_2 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 -} -scom 0x80000D7C0301143f { # DATA_BIT_DISABLE0_RP1_P0_3 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 -} -scom 0x8000117C0301143f { # DATA_BIT_DISABLE0_RP1_P0_4 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255) ; # invalid rank pair1 -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0 0x27C 0x8000027c0301143f -scom 0x8000027C0301143f { # DATA_BIT_DISABLE0_RP2_P0_0 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 -} -scom 0x8000067C0301143f { # DATA_BIT_DISABLE0_RP2_P0_1 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 -} -scom 0x80000A7C0301143f { # DATA_BIT_DISABLE0_RP2_P0_2 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 -} -scom 0x80000E7C0301143f { # DATA_BIT_DISABLE0_RP2_P0_3 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 -} -scom 0x8000127C0301143f { # DATA_BIT_DISABLE0_RP2_P0_4 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255) ; # invalid rank pair2 -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0 0x37C 0x8000037c0301143f -scom 0x8000037C0301143f { # DATA_BIT_DISABLE0_RP3_P0_0 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 -} -scom 0x8000077C0301143f { # DATA_BIT_DISABLE0_RP3_P0_1 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 -} -scom 0x80000B7C0301143f { # DATA_BIT_DISABLE0_RP3_P0_2 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 -} -scom 0x80000F7C0301143f { # DATA_BIT_DISABLE0_RP3_P0_3 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 -} -scom 0x8000137C0301143f { # DATA_BIT_DISABLE0_RP3_P0_4 - bits , scom_data , expr ; # bits 0:15 - 48:55 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 - 56:63 , 0xFF , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255) ; # invalid rank pair3 -} - -# Port1, MBA01 = instance 2 -# 56:63 , 0xFF , ((def_no_spare) && (def_is_mba01)) ; # disable spare bits -# Port1, MBA23 = instance 1 -# 56:63 , 0xFF , ((def_no_spare) && (def_is_mba23)) ; # disable spare bits - +# #--------------------------------------------------------------------------- # DP18 Data Bit Disable 1 default=0 # @@ -3483,34 +4207,22 @@ scom 0x8000137C0301143f { # DATA_BIT_DISABLE0_RP3_P0_4 # # DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_0 0x07D 0x8000007d0301143f # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_L2 -#scom 0x80007D000301143f { # DATA_BIT_DISABLE1_RP0_P0_0 -# bits , scom_data , expr ; # bits 16:23 -# 48:55 , 0x00 , any ; # ATTR_MSS_BAD_BIT_MASK[2][2][8][10] -# 56:63 , 0x00 , any ; # reserved -#} #--------------------------------------------------------------------------- # ADR BIT ENABLE P[0:1] ADR[0:3] default=0 # -# Note: refined this so that bits 12:15 not used in ADR[0:1], -# and bits 14:15 not used in ADR[2:3]. +# Turn off of deconfigured the ports handled in a clean up procedure # # DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR0 0x000 0x800040000301143f -# DPHY01.DDRPHY_ADR_BIT_ENABLE_P0_ADR0 from (alias spydef) -#scom 0x800(0,1)(40,44,48,4c)000301143f { # _P[0:1]_ADR[0:3] -# scom 0x800(0,1)7C000301143F { # _P[0:1]_ADR[0:3] via broadcast -# bits , scom_data ; -# 48:63 , 0xFFFF ; # enable all ADR bits -# } - -# need to turn off if deconfiguring the ports, should be handled in a -# clean up procedure +# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.P_REG_A_00_L2 scom 0x800(040,044,140,144)000301143F { # _P[0:1]_ADR[0:1] +# 0:47 , 0x000000000000 ; # reserved bits , scom_data ; 48:63 , 0xFFF0 ; # bits 12:15 not used in ADR[0:1] } scom 0x800(048,04C,148,14C)000301143F { # _P[0:1]_ADR[2:3] bits , scom_data ; +# 0:47 , 0x000000000000 ; # reserved 48:63 , 0xFFFC ; # 14:15 not used in ADR[2:3] } @@ -3538,98 +4250,438 @@ scom 0x800(048,04C,148,14C)000301143F { # _P[0:1]_ADR[2:3] # 49:55 = value0, 57:63 = value1, # 0x40 = 64 (for single data rate), 0x20 = 32 (for double data rate) # -# ------------- Port 0 --------------------------------------------- # [01:23] [0:7] [0:1] [0:3] -# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR0 0x004 0x800040090301143f +# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0 0x004-00B 0x800040040301143f # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_09_L2 -scom 0x800040090301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba01) ; # lane 10:11, clk0_p/n -} -# DPHY01.DDRPHY_ADR_DELAY5_P0_ADR2 from (alias spydef) -# DPHY23_DDRPHY_ADR_DELAY5_P0_ADR2 -scom 0x800048090301143F { - # ------------- Port 0 & 2 ------------------------------------- - bits , scom_data , expr ; - # for port 0 & port 2, lane 10:11, Port0=clk1_n/p, Port2=clk0_n/p - 48:63 , 0x4040 , any ; # for both mba01 & mba23 - #48:63 , 0x4040 , ((def_is_mba01) || (def_is_mba23)) ; -} -# DPHY01.DDRPHY_ADR_DELAY2_P0_ADR2 from (alias spydef) -scom 0x800048060301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba01) ; # lane 4:5, clk2_p/n -} -# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2 from (alias spydef) -scom 0x8000480A0301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba01) ; # lane 12:13, clk3_n/p -} - -# ------------- Port 2 --------------------------------------------- -# DPHY23_DDRPHY_ADR_DELAY3_P0_ADR0 -scom 0x800040070301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba23) ; # lane 6:7, clk1_p/n - 48:63 , 0x0000 , any ; # mba01 -} -#DPHY23_DDRPHY_ADR_DELAY1_P0_ADR3 -scom 0x80004C050301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba23) ; # lane 2:3, clk2_p/n - 48:63 , 0x0000 , any ; # mba01 -} -# DPHY23_DDRPHY_ADR_DELAY4_P0_ADR0 -scom 0x800040080301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba23) ; # lane 8:9, clk3_p/n - 48:63 , 0x0000 , any ; # mba01 -} - -# ------------- Port 1 --------------------------------------------- -# DPHY01.DDRPHY_ADR_DELAY1_P1_ADR3 from (alias spydef) -# DPHY23_DDRPHY_ADR_DELAY1_P1_ADR3 -scom 0x80014C050301143F { - # ------------- Port 1 & 3 ------------------------------------- - bits , scom_data , expr ; - # lane 2:3, Port1=clk0_n/p, Port3=clk0_n/p - 48:63 , 0x4040 , any ; # for mba01 & mba23 - #48:63 , 0x4040 , ((def_is_mba01) || (def_is_mba23)) ; -} -# DPHY01.DDRPHY_ADR_DELAY4_P1_ADR2 from (alias spydef) -scom 0x800148080301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba01) ; # lane 8:9, clk1_p/n -} -# DPHY01.DDRPHY_ADR_DELAY0_P1_ADR0 from (alias spydef) -scom 0x800140040301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba01) ; # lane 0:1, clk2_n/p -} -# DPHY01.DDRPHY_ADR_DELAY1_P1_ADR0 from (alias spydef) -scom 0x800140050301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba01) ; # lane 2:3, clk3_n/p -} - -# ------------- Port 3 --------------------------------------------- -# DPHY23_DDRPHY_ADR_DELAY6_P1_ADR2 -scom 0x8001480A0301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba23) ; # lane 12:13, clk1_n/p - 48:63 , 0x0000 , any ; # -} -# DPHY23_DDRPHY_ADR_DELAY5_P1_ADR0 -scom 0x800140090301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba23) ; # lane 10:11, clk2_p/n - 48:63 , 0x0000 , any ; # -} -# DPHY23_DDRPHY_ADR_DELAY5_P1_ADR2 -scom 0x800148090301143F { - bits , scom_data , expr ; - 48:63 , 0x4040 , (def_is_mba23) ; # lane 10:11, clk3_n/p - 48:63 , 0x0000 , any ; # +#==================================================================================== +# PORT 0 / 2 +#==================================================================================== +#-- Port 0/2 ADR 0 ------------------------------------------------------------ +scom 0x800040040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L0 , A1_CKE1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L1 , A0_CS3n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L0 , C0_CS0n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba23) ; # P2 L1 , C_A3 +} +scom 0x800040050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L2 , A1_CKE0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L3 , A0_ODT0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L2 , C1_CS3n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba23) ; # P2 L3 , C_RASn +} +scom 0x800040060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P0_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba01) ; # P0 L4 , A_A15 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba01) ; # P0 L5 , A_PAR + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba23) ; # P2 L4 , C_A12 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba23) ; # P2 L5 , C_A7 +} +scom 0x800040070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L6 , A0_CKE1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L7 , A0_CS1n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L6 , C0_CLK1_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L7 , C0_CLK1_n +} +scom 0x800040080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L8 , A0_CKE0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L9 , A1_ODT0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L8 , C1_CLK1_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L9 , C1_CLK1_n +} +scom 0x800040090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L10, A0_CLK0_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L11, A0_CLK0_n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L10, C1_CKE2 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L11, C0_CKE2 +} +#-- Port 0/2 ADR 1 ------------------------------------------------------------ +scom 0x800044040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L0 , A0_CS0n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L1 , A1_CKE3 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba23) ; # P2 L0 , C_BA2 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L1 , C1_CKE1 +} +scom 0x800044050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L2 , A1_ODT1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba01) ; # P0 L3 , A_A2 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L2 , C0_ODT1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba23) ; # P2 L3 , C_WEn +} +scom 0x800044060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P0_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba01) ; # P0 L4 , A_A6 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba01) ; # P0 L5 , A_A1 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L4 , C0_CS1n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba23) ; # P2 L5 , C_A11 +} +scom 0x800044070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba01) ; # P0 L6 , A_A14 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L7 , A0_CKE2 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L7 , C0_CS2n +} +scom 0x800044080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L8 , A1_CS2n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L9 , A1_CKE2 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L8 , C0_ODT0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba23) ; # P2 L9 , C_A8 +} +scom 0x800044090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba01) ; # P0 L10, A_A4 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba01) ; # P0 L11, A_RASn + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba23) ; # P2 L10, C_A5 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L11, C1_CS0n +} +#-- Port 0/2 ADR 2 ------------------------------------------------------------ +scom 0x800048040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba01) ; # P0 L0 , A_A12 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba01) ; # P0 L1 , A_A0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba23) ; # P2 L0 , C_A1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba23) ; # P2 L1 , C_A6 +} +scom 0x800048050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L2 , A0_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L3 , A1_CS3n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba23) ; # P2 L2 , C_A13 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L3 , C0_CKE0 +} +scom 0x800048060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L4 , A1_CLK0_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L5 , A1_CLK0_n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L4 , C1_ODT0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L5 , C1_CS1n +} +scom 0x800048070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L6 , A0_ODT1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L7 , A1_CS0n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L7 , C1_CKE0 +} +scom 0x800048080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L8 , A1_CS1n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba01) ; # P0 L9 , A_A10 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba23) ; # P2 L8 , C_A0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba23) ; # P2 L9 , C_BA1 +} +scom 0x800048090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L12, A0_CLK1_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L13, A0_CLK1_p + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L12, C0_CLK0_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L13, C0_CLK0_p +} +scom 0x8000480A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L12, A1_CLK1_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L13, A1_CLK1_p + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L12, C1_CS2n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba23) ; # P2 L13, C_A10 +} +#-- Port 0/2 ADR 3 ------------------------------------------------------------ +scom 0x80004C040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba01) ; # P0 L0 , A_A13 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba01) ; # P0 L1 , A_BA0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba23) ; # P2 L0 , C_PAR + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L1 , C1_ODT1 +} +scom 0x80004C050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba01) ; # P0 L2 , A_WEn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L3 , A0_CS2n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L2 , C1_CLK0_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L3 , C1_CLK0_n +} +scom 0x80004C060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba01) ; # P0 L4 , A_BA1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba01) ; # P0 L5 , A_CASn + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba23) ; # P2 L4 , C_A14 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba23) ; # P2 L5 , C_A9 +} +scom 0x80004C070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba01) ; # P0 L6 , A_A5 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba01) ; # P0 L7 , A_A3 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba23) ; # P2 L6 , C_ACTn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba23) ; # P2 L7 , C_A2 +} +scom 0x80004C080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba01) ; # P0 L8 , A_BA2 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba01) ; # P0 L9 , A_A11 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L8 , C1_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba23) ; # P2 L9 , C_A15 +} +scom 0x80004C090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba01) ; # P0 L12, A_A7 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba01) ; # P0 L13, A_ACTn + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba23) ; # P2 L12, C_BA0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba23) ; # P2 L13, C_CASn +} +scom 0x80004C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba01) ; # P0 L12, A_A9 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba01) ; # P0 L13, A_A8 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba23) ; # P2 L12, C_A4 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L13, C0_CS3n +} +#==================================================================================== +# PORT 1 / 3 +#==================================================================================== +#-- Port 1/3 ADR 0------------------------------------------------------------ +scom 0x800140040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L0 , B1_CLK0_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L1 , B1_CLK0_p + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L0 , D1_CKE1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba23) ; # P3 L1 , D_BA2 +} +scom 0x800140050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L2 , B1_CLK1_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L3 , B1_CLK1_p + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba23) ; # P3 L2 , D_A1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba23) ; # P3 L3 , D_A5 +} +scom 0x800140060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P1_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L4 , B0_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L5 , B0_CS3n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba23) ; # P3 L4 , D_A12 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba23) ; # P3 L5 , D_BA0 +} +scom 0x800140070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba01) ; # P1 L6 , B_BA0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT1 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE2 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L7 , D1_CS1n +} +scom 0x800140080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L8 , B1_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba01) ; # P1 L9 , B_A15 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L9 , D0_CS2n +} +scom 0x800140090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR0 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L10, B1_CS2n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L11, B0_CKE1 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L10, D1_CLK0_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L11, D1_CLK0_n +} +#-- Port 1/3 ADR 1 ------------------------------------------------------------ +scom 0x800144040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L0 , B0_CKE2 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba01) ; # P1 L1 , B_A7 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba23) ; # P3 L0 , D_A8 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba23) ; # P3 L1 , D_A13 +} +scom 0x800144050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba01) ; # P1 L2 , B_A10 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L3 , B1_CKE1 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L2 , D0_ODT1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba23) ; # P3 L3 , D_PAR +} +scom 0x800144060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P1_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L4 , B0_CS1n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba01) ; # P1 L5 , B_A8 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L4 , D1_CS0n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba23) ; # P3 L5 , D_A11 +} +scom 0x800144070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba01) ; # P1 L6 , B_A6 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L7 , B1_CS3n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L6 , D0_CKE1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba23) ; # P3 L7 , D_WEn +} +scom 0x800144080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba01) ; # P1 L8 , B_A4 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L9 , B1_CS1n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L9 , D1_ODT0 +} +scom 0x800144090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR1 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba01) ; # P1 L10, B_A1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba01) ; # P1 L11, B_BA1 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba23) ; # P3 L10, D_RASn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L11, D0_CS1n +} +#-- Port 1/3 ADR 2 ------------------------------------------------------------ +scom 0x800148040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L0 , B0_CS2n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L1 , B0_ODT0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L0 , D0_CS0n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba23) ; # P3 L1 , D_A10 +} +scom 0x800148050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba01) ; # P1 L2 , B_WEn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba01) ; # P1 L3 , B_A2 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba23) ; # P3 L2 , D_A4 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L3 , D1_CS3n +} +scom 0x800148060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L4 , B0_ODT1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L5 , B0_CS0n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba23) ; # P3 L4 , D_ACTn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba23) ; # P3 L5 , D_A9 +} +scom 0x800148070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba01) ; # P1 L6 , B_A3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba01) ; # P1 L7 , B_A0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE3 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L7 , D1_CKE0 +} +scom 0x800148080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L8 , B0_CLK1_p + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L9 , B0_CLK1_n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L8 , D0_CS3n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba23) ; # P3 L9 , D_A2 +} +scom 0x800148090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba01) ; # P1 L10, B_CASn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L11, B1_CS0n + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L10, D1_CLK1_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L11, D1_CLK1_p +} +scom 0x8001480A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P1_ADR2 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L12, B1_CKE0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba01) ; # P1 L13, B_A12 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L12, D0_CLK1_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L13, D0_CLK1_p +} +#-- Port 1/3 ADR 3 ------------------------------------------------------------ +scom 0x80014C040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba01) ; # P1 L0 , B_A11 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L1 , B0_CKE0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L0 , D1_CS2n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L1 , D0_ODT0 +} +scom 0x80014C050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L2 , B0_CLK0_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L3 , B0_CLK0_p + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L2 , D0_CLK0_n + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L3 , D0_CLK0_p +} +scom 0x80014C060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba01) ; # P1 L4 , B_A13 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba01) ; # P1 L5 , B_A14 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba23) ; # P3 L4 , D_A6 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L5 , D1_ODT1 +} +scom 0x80014C070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L6 , B1_CKE2 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT0 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba23) ; # P3 L6 , D_A0 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba23) ; # P3 L7 , D_CASn +} +scom 0x80014C080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba01) ; # P1 L8 , B_A9 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba01) ; # P1 L9 , B_BA2 + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba23) ; # P3 L8 , D_A14 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba23) ; # P3 L9 , D_A3 +} +scom 0x80014C090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba01) ; # P1 L10, B_RASn + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba01) ; # P1 L11, B_ACTn + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba23) ; # P3 L10, D_A7 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba23) ; # P3 L11, D_A15 +} +scom 0x80014C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P1_ADR3 + bits , scom_data , expr ; +# 0:47 , 0x000000000000 , any ; # reserved + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba01) ; # P1 L12, B_A5 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba01) ; # P1 L13, B_PAR + 48:55 , (ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba23) ; # P3 L12, D_BA1 + 56:63 , (ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L13, D0_CKE2 } #================================================================================ @@ -3645,60 +4697,70 @@ scom 0x800148090301143F { # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_01_L2 scom 0x800040010301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:55 , 0x04 , (def_is_mba01) ; # lane 10:11(clk0) # ------------- Port 2 ------------------------------------- # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 48:55 , 0x18 , (def_is_mba23) ; # lane 6:7(clk1), 8:9(clk3) +# 56:63 , 0x00 , any ; # reserved } -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 from (alias spydef) +# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 scom 0x800048010301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:55 , 0x26 , (def_is_mba01) ; # lane 4:5(clk2), 10:11(clk1), 12:13(clk3) # ------------- Port 2 ------------------------------------- # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 48:55 , 0x04 , (def_is_mba23) ; # lane 10:11(clk0) +# 56:63 , 0x00 , any ; # reserved } # ------------- Port 2 --------------------------------------------- # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3 scom 0x80004C010301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:55 , 0x40 , (def_is_mba23) ; # lane 2:3(clk2) 48:55 , 0x00 , any ; # for mba01 +# 56:63 , 0x00 , any ; # reserved } # ------------- Port 1 --------------------------------------------- -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 from (alias spydef) +# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 scom 0x800140010301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:55 , 0xC0 , (def_is_mba01) ; # lane 0:1(clk2), 2:3(clk3) # ------------- Port 3 ------------------------------------- # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 48:55 , 0x04 , (def_is_mba23) ; # lane 10:11(clk2) +# 56:63 , 0x00 , any ; # reserved } -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 from (alias spydef) +# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 scom 0x800148010301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:55 , 0x08 , (def_is_mba01) ; # lane 8:9(clk1) # ------------- Port 3 ------------------------------------- # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 48:55 , 0x06 , (def_is_mba23) ; # lane 10:11(clk3), 12:13(clk1) +# 56:63 , 0x00 , any ; # reserved } -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 from (alias spydef) +# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 scom 0x80014C010301143F { bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48:55 , 0x40 , (def_is_mba01) ; # lane 2:3(clk0) # ------------- Port 3 ------------------------------------- # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 48:55 , 0x40 , (def_is_mba23) ; # lane 2:3(clk0) +# 56:63 , 0x00 , any ; # reserved } # !! need updates to these clock registers from PHY / SIM team # set to 0x8070, reset seq sets it to 0x8024 #--------------------------------------------------------------------------------------- -# ADR SYSCLK settings default=0x8074 -# -# DPHY01.DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 from (alias spydef) +# ADR SYSCLK settings default=0x8074 # # Controls the circuit which aligns the internal SysClk to the incoming dphy_nclk clock. # @@ -3707,45 +4769,63 @@ scom 0x80014C010301143F { #scom 0x800(0,1)(80,84)320301143F { # _P[0:1]_ADR32S[0:1] scom 0x800(0,1)BC320301143F { # _P[0:1]_ADR32S[0:1] via broadcast bits , scom_data , expr ; - 48 , 0b0 , (def_is_sim) ; # made to match dials +# 0:47 , 0x000000000000, any ; # reserved +# old dials value = 0x0080 48 , 0b1 , any ; # ADR32_SYSCLK_ENABLE 49:55 , 0b0000000 , any ; # ADR32_SYSCLK_ROT_OVERRIDE - 56 , 0b1 , (def_is_sim) ; # made to match dials 56 , 0b0 , any ; # ADR32_SYSCLK_ROT_OVERRIDE_EN - 57 , 0b0 , (def_is_sim) ; # made to match dials 57 , 0b1 , any ; # ADR32_SYSCLK_PHASE_ALIGN_RESET - 58 , 0b0 , (def_is_sim) ; # made to match dials 58 , 0b1 , any ; # ADR32_SYSCLK_PHASE_CNTL_EN - 59 , 0b0 , (def_is_sim) ; # made to match dials 59 , 0b1 , any ; # ADR32_SYSCLK_PHASE_DEFAULT_EN 60 , 0b0 , any ; # ADR32_SYSCLK_POS_EDGE_ALIGN - 61 , 0b0 , any ; # ADR32_CONTINUOUS_UPDATE +# recent 7/3 + 61 , 0b1 , any ; # ADR32_CONTINUOUS_UPDATE 62:63 , 0b00 , any ; # CE0DLTVCC, must be '00'b } # --------------------------------------------------------------------------------------- -# DPHY01.DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 from (alias spydef) +# ADR WRClk Phase Rotator Offset Value default=0 # -# !!NOTE different depending on EC level +# !! NOTE different depending on EC level # # ADR Phase Rotator Static Offset value used to determine the # Phase of the WrClk with respect to SysClk. Adjusts for race # condition between combinatorial logic for WrClk to SysClk. # -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_33_L2 # [01:23] [0:1] [0:1] # DPHY01_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 0x033 0x800080330301143f +# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_33_L2 +# 0x800080330301143F 0x800084330301143F 0x800180330301143F 0x800184330301143F #scom 0x800(0,1)(80,84)330301143F { # _P[0:1]_ADR32S[0:1] scom 0x800(0,1)BC330301143F { # _P[0:1]_ADR32S[0:1] via broadcast - bits , scom_data , expr ; # !!NOTE different depending on EC level - 48:55 , def_ADR32_TSYS_WRCLK , any ; # ADR32_TSYS_WRCLK for sim set to 0x60 -# 56:63 , 0x00 , any ; # reserved + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# 48 , 0b0 , any ; # reserved + # !! NOTE different depending on EC level, system voltage too? + # value in the scom_data field is right aligned + 48:55 , 0x60 , (def_is_sim) ; # ADR32_TSYS_WRCLK sim set to 0x60 +# below is for fast process parts +# 48:55 , 0x15 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (21) +# 48:55 , 0x19 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (25) +# 48:55 , 0x1E , any ; # 1866 Mbps (30) +# group below is for most parts process... +## 48:55 , 0x22 , (CEN.ATTR_MSS_FREQ < 1191) ; # 1066 Mbps, 120 +# 48:55 , 0x22 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (34) +# 48:55 , 0x28 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (40) +# 48:55 , 0x2F , any ; # 1866 Mbps (47) +# below is for slow process parts +# 48:55 , 0x2D , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (45) +# 48:55 , 0x35 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (53) +# 48:55 , 0x3E , any ; # 1866 Mbps (62) +#-------- debug ----------------------------- + 48:55 , 0x70 , any ; +# 56:63 , 0x00 , any ; # reserved } # --------------------------------------------------------------------------------------- @@ -3753,7 +4833,7 @@ scom 0x800(0,1)BC330301143F { # _P[0:1]_ADR32S[0:1] via broadcast # --------------------------------------------------------------------------------------- # DPHY01.DDRPHY_DP18_WRCLK_PR_P0_0 default=0 # -# !!NOTE different depending on EC level +# !! NOTE different depending on EC level # # DP18 Phase Rotator Static Offset value used to # determine the Phase of the WrClk with respect to SysClk. @@ -3763,18 +4843,34 @@ scom 0x800(0,1)BC330301143F { # _P[0:1]_ADR32S[0:1] via broadcast # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_WRCLK_PR_L2 #scom 0x800(0,1)(00,04,08,0C,10)740301143F { #_P[0:1]_[0:4] scom 0x800(0,1)3C740301143F { #_P[0:1]_[0:4] via broadcast - bits , scom_data , expr ; # !!NOTE different depending on EC level -# 48 , 0b0 , any ; # reserved -# below yields 0x3000 in register instead of 0x6000 if not right aligned. -# 49:55 , 0b1100000 , (def_is_sim) ; # DP18_TSYS_WRCLK # for sim set to 0x60 - 49:55 , def_DP18_TSYS_WRCLK , any ; # DP18_TSYS_WRCLK -# 56:63 , 0x00 , any ; # reserved + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved +# 48 , 0b0 , any ; # reserved + # !! NOTE different depending on EC level + # value in the scom_data field is right aligned + 48:55 , 0x60 , (def_is_sim) ; # DP18_TSYS_WRCLK sim set to 0x60 +# below is for fast process parts +# 48:55 , 0x14 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (20) +# 48:55 , 0x18 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (24) +# 48:55 , 0x1C , any ; # 1866 Mbps (28) +# group below is for most parts process... +## 48:55 , 0x78 , (CEN.ATTR_MSS_FREQ < 1191) ; # 1066 Mbps +# 48:55 , 0x20 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (32) +# 48:55 , 0x27 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (39) +# 48:55 , 0x2D , any ; # 1866 Mbps (45) +# below is for slow process parts +# 48:55 , 0x2C , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (44) +# 48:55 , 0x35 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (53) +# 48:55 , 0x3E , any ; # 1866 Mbps (62) +#-------- debug ----------------------------- + 48:55 , 0x6B , any ; +# 56:63 , 0x00 , any ; # reserved } # --------------------------------------------------------------------------------------- # --- DP18 SYSCLK_PR P[0:1]_[0:4] Phase Rotator --------------------------- # --------------------------------------------------------------------------------------- -# DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0 from (alias spydef) default=0x8070 +# DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0 default=0x8070 # # to Align bang-bang # @@ -3790,6 +4886,7 @@ scom 0x800(0,1)3C740301143F { #_P[0:1]_[0:4] via broadcast #scom 0x800(0,1)(00,04,08,0C,10)070301143F { #_P[0:1]_[0:4] scom 0x800(0,1)3C070301143F { #_P[0:1]_[0:4] via broadcast bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved 48 , 0b1 , any ; # DP18_SYSCLK_ENABLE 49:55 , 0b0000000 , any ; # DP18_SYSCLK_ROT_OVERRIDE @@ -3821,8 +4918,66 @@ scom 0x800(0,1)3C070301143F { #_P[0:1]_[0:4] via broadcast # These are settings for the read and write clock enables of the rank pair for # x4 & x8 DRAM devices with and without spare DRAMs. # +# Configuration Requirements: +# 1) If bit 49, 50, or 51 are set, either bit 48 or 52 must also be set. +# 2) If bit 52 is set, then bit 49 or 53 must also be set unless bit 52 was only set to satisfy requirement 1. +# 3) If bit 55 is set, then bit 50, 54, or 56 must also be set. +# 4) If bit 56 is set, then bit 51, 55, or 57 must also be set unless bit 56 was only set to satisfy requirement 3. +# +# [X:Y] represent DP18 lanes(24) +# lanes 0:15 used for dq bits +# lanes 16:23 used for dqs signal pairs (16:17, 18:19, 20:21, 22:23) +# +# if x4 & no swizzle if x8 and no swizzle +# quad0 = dq[0:3] clk16 = dqs[16:17] clk16 = dqs[16:17] +# quad1 = dq[4:7] clk18 = dqs[18:19] clk16 = dqs[16:17] +# quad2 = dq[8:11] clk20 = dqs[20:21] clk20 = dqs[20:21] +# quad3 = dq[12:15] clk22 = dqs[22:23] clk20 = dqs[20:21] +# +# or another way to look at it... +# +# for x4: +# dqs lane pairs 16/17 18/19 20/21 22/23 +# dq quad nibbles 0 1 2 3 // no swizzle +# 1 0 2 3 // swizzle lane pairs 16/17 with 18/19 +# 0 1 3 2 // swizzle lane pairs 20/21 with 22/23 +# 1 0 3 2 // swizzle lane pairs 16/17 with 18/19 & 20/21 with 22/23 +# +# for x8: +# dqs lane pairs 16/17 18/19 20/21 22/23 +# dq quad nibbles 0:1 n/a 2:3 n/a // no swizzle +# n/a 0:1 2:3 n/a // swizzle lane pairs 16/17 with 18/19 +# 0:1 n/a n/a 2:3 // swizzle lane pairs 20/21 with 22/23 +# n/a 0:1 n/a 2:3 // swizzle lane pairs 16/17 with 18/19 & 20/21 with 22/23 +# +# quadx_clk# 16 18 20 22 +# quad# 0 1 2 3 0 1 2 3 2 3 +# ---------------------------------- +# bits 0 1 2 3 4 5 6 7 8 9 10 11 (10:15 unused) +# ============================================================== +# possible spare (x4) +# 0x8640 1 0 0 0 0 1 1 0 0 1 0 0 = x4 no-swizzle, q0=16, q1=18, q2=20, q3=22 +# 0x4A40 0 1 0 0 1 0 1 0 0 1 0 0 = x4 swizzle quad0/1, q0=18, q1=16, q2=20, q3=22 +# 0x8580 1 0 0 0 0 1 0 1 1 0 0 0 = x4 swizzle quad2/3, q0=16, q1=18, q2=22, q3=20 +# 0x4980 0 1 0 0 1 0 0 1 1 0 0 0 = x4 swizzle quad0/1 & 2/3, q0=18, q1=16, q2=22, q3=20 +# +# no spare (x4) +# 0x8400 1 0 0 0 0 1 0 0 0 0 0 0 = x4 no-swizzle, q0=16, q1=18, q2=n/a, q3=n/a +# 0x4800 0 1 0 0 1 0 0 0 0 0 0 0 = x4 swizzle quad0/1, q0=18, q1=16, q2=n/a, q3=n/a +# +# possible spare (x8) +# 0xC300 1 1 0 0 0 0 1 1 0 0 0 0 = x8 no-swizzle, q0:1=16, q2:3=20 +# 0x0F00 0 0 0 0 1 1 1 1 0 0 0 0 = x8 swizzle quad0/1, q0:1=18, q2:3=20 +# 0xC0C0 1 1 0 0 0 0 0 0 1 1 0 0 = x8 swizzle quad2/3, q0:1=16, q2:3=22 +# 0x0CC0 0 0 0 0 1 1 0 0 1 1 0 0 = x8 swizzle quad0/1 & 2/3, q0:1=18, q2:3=22 +# +# no spare (x8) +# 0xC000 1 1 0 0 0 0 0 0 0 0 0 0 = x8 no swizzle +# 0x0C00 0 0 0 0 1 1 0 0 0 0 0 0 = x8 swizzle quad0/1 +# +# # For Centaur: -# Spares on P0_1, P1_2, P2_4, P3_1, DQS in lanes 2:3, DQ in lanes 8:15 +# Spares on P0_1, P1_2, P2_4, P3_1, DQ in lanes 0:15, DQS in lanes 16:23 # # DP18 Read Clock Enable & Selection RP0 # [01:23] PAIR[0:3]_P[0:1]_[0:4] @@ -3843,149 +4998,173 @@ scom 0x800(0,1)3C070301143F { #_P[0:1]_[0:4] via broadcast # # instance _0=00, _1=04, _2=08, _3=0C, _4=10 # RANK_PAIR[0:3], RP[0:3] _P0_0 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 (4) -# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_0 (5) +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 (4) 0x800000040301143F +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1 (4) 0x800004040301143F +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2 (4) 0x800008040301143F +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3 (4) 0x80000C040301143F +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4 (4) 0x800010040301143F +# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_0 (5) 0x800000050301143F +# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_1 (5) 0x800004050301143F +# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_2 (5) 0x800008050301143F +# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_3 (5) 0x80000C050301143F +# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_4 (5) 0x800010050301143F scom 0x8000008(4,5)0301143F { # _RP[0:3] via broadcast bit # P0_0 - bits , scom_data , expr ; - 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad2/3 + 48:63 , 0xC0C0 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad 2/3 + 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle # P2_0 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P0_1 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1 0x800004840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1 0x800004850301143F scom 0x8000048(4,5)0301143F { # _RP[0:3] via broadcast bit # P0_1 - bits , scom_data , expr ; - 48:63 , 0x8580 , ((def_is_mba01) && (def_has_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x8400 , ((def_is_mba01) && (def_no_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_has_spare) && (def_is_x8)) ; # x8 - 48:63 , 0x0C00 , ((def_is_mba01) && (def_no_spare) && (def_is_x8)) ; # x8 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8580 , ((def_is_mba01) && (def_has_spare) && (def_is_x4)) ; # x4 spare swizzle quad2/3 + 48:63 , 0x8400 , ((def_is_mba01) && (def_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle + 48:63 , 0x0CC0 , ((def_is_mba01) && (def_has_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 + 48:63 , 0x0C00 , ((def_is_mba01) && (def_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 # P2_1 - 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad2/3 + 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P0_2 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2 0x800008840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2 0x800008850301143F scom 0x8000088(4,5)0301143F { # _RP[0:3] via broadcast bit # P0_2 bits , scom_data , expr ; - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_is_x8)) ; # x8 +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0x0CC0 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 # P2_2 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0x0CC0 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0x0CC0 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P0_3 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3 0x80000C840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3 0x80000C850301143F scom 0x80000C8(4,5)0301143F { # _RP[0:3] via broadcast bit # P0_3 - bits , scom_data , expr ; - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_is_x8)) ; # x8 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad0/1 + 48:63 , 0x0CC0 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 # P2_3 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0xC0C0 , ((def_is_mba23) && (def_is_x8)) ; # x8 - 48:63 , 0x0000 , any ; + 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0xC0C0 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad2/3 + 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P0_4 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4 0x800010840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4 0x800010850301143F scom 0x8000108(4,5)0301143F { # _RP[0:3] via broadcast bit # P0_4 bits , scom_data , expr ; - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 # P2_4 - 48:63 , 0x8640 , ((def_is_mba23) && (def_has_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x8400 , ((def_is_mba23) && (def_no_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x0F00 , ((def_is_mba23) && (def_has_spare) && (def_is_x8)) ; # x8 - 48:63 , 0x0C00 , ((def_is_mba23) && (def_no_spare) && (def_is_x8)) ; # x8 - 48:63 , 0x0000 , any ; + 48:63 , 0x8640 , ((def_is_mba23) && (def_has_spare) && (def_is_x4)) ; # x4 spare no swizzle + 48:63 , 0x8400 , ((def_is_mba23) && (def_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle + 48:63 , 0x0F00 , ((def_is_mba23) && (def_has_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 + 48:63 , 0x0C00 , ((def_is_mba23) && (def_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 + 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P1_0 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_0 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0 0x800100840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_0 0x800100850301143F scom 0x8001008(4,5)0301143F { # _RP[0:3] via broadcast bit # P1_0 - bits , scom_data , expr ; - 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad0/1 + 48:63 , 0xC0C0 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad2/3 + 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 # P3_0 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3]_, P1_1 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1 0x800104840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1 0x800104850301143F scom 0x8001048(4,5)0301143F { # _RP[0:3] via broadcast bit # P1_1 - bits , scom_data , expr ; - 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4) && (def_is_type1)) ; # x4 no swizzle + 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad0/1 + 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle # P3_1 - 48:63 , 0x8640 , ((def_is_mba23) && (def_has_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x8400 , ((def_is_mba23) && (def_no_spare) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba23) && (def_has_spare) && (def_is_x8)) ; # x8 - 48:63 , 0xC000 , ((def_is_mba23) && (def_no_spare) && (def_is_x8)) ; # x8 - 48:63 , 0x0000 , any ; + 48:63 , 0x8640 , ((def_is_mba23) && (def_has_spare) && (def_is_x4)) ; # x4 spare no swizzle + 48:63 , 0x8400 , ((def_is_mba23) && (def_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle + 48:63 , 0xC300 , ((def_is_mba23) && (def_has_spare) && (def_is_x8)) ; # x8 no swizzle + 48:63 , 0xC000 , ((def_is_mba23) && (def_no_spare) && (def_is_x8)) ; # x8 no swizzle + 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P1_2 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2 0x800108840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2 0x800108850301143F scom 0x8001088(4,5)0301143F { # _RP[0:3] via broadcast bit # P1_2 bits , scom_data , expr ; - 48:63 , 0x8640 , ((def_is_mba01) && (def_has_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x8400 , ((def_is_mba01) && (def_no_spare) && (def_is_x4)) ; # x4 - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_has_spare) && (def_is_x8)) ; # x8 - 48:63 , 0x0C00 , ((def_is_mba01) && (def_no_spare) && (def_is_x8)) ; # x8 +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8640 , ((def_is_mba01) && (def_has_spare) && (def_is_x4)) ; # x4 spare no swizzle + 48:63 , 0x8400 , ((def_is_mba01) && (def_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle + 48:63 , 0x0CC0 , ((def_is_mba01) && (def_has_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 + 48:63 , 0x0C00 , ((def_is_mba01) && (def_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 # P3_2 - 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad2/3 + 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P1_3 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3 0x80010C840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3 0x80010C850301143F scom 0x80010C8(4,5)0301143F { # _RP[0:3] via broadcast bit # P1_3 - bits , scom_data , expr ; - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 + bits , scom_data , expr ; +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0xC0C0 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad2/3 + 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle # P3_3 - 48:63 , 0x4A40 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x4A40 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad0/1 + 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle 48:63 , 0x0000 , any ; } # RANK_PAIR[0:3], RP[0:3] _P1_4 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4 +# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4 0x800110840301143F +# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4 0x800110850301143F scom 0x8001108(4,5)0301143F { # _RP[0:3] via broadcast bit # P1_4 bits , scom_data , expr ; - 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 +# 0:47 , 0x000000000000, any ; # reserved + 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad2/3 + 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle # P3_4 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 - 48:63 , 0x0CC0 , ((def_is_mba23) && (def_is_x8)) ; # x8 + 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle + 48:63 , 0x0CC0 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 48:63 , 0x0000 , any ; } + |
