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author | Patrick Williams <patrick@stwcx.xyz> | 2017-03-29 07:40:19 -0500 |
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committer | GitHub <noreply@github.com> | 2017-03-29 07:40:19 -0500 |
commit | ffd86801c045a8514070acd057157b542b126cff (patch) | |
tree | 30cc9c67ed0fa760870515f74735b7532b34a739 | |
parent | d8a1bac8634033a3edd4e9a22455f97318718f43 (diff) | |
parent | 565c21a4d713776676a1b847e68b60e222abfbf6 (diff) | |
download | ppe42-gcc-ffd86801c045a8514070acd057157b542b126cff.tar.gz ppe42-gcc-ffd86801c045a8514070acd057157b542b126cff.zip |
Merge pull request #3 from dgilbert999/gcc-4_9_2-ppe42
Fix compile issue when compiling with gcc 6
-rw-r--r-- | gcc/config/rs6000/option-defaults.h | 4 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 124 | ||||
-rw-r--r-- | gcc/cp/cfns.gperf | 2 | ||||
-rw-r--r-- | gcc/cp/cfns.h | 2 |
4 files changed, 123 insertions, 9 deletions
diff --git a/gcc/config/rs6000/option-defaults.h b/gcc/config/rs6000/option-defaults.h index dc4cce0d6ce..043dbcc91e6 100644 --- a/gcc/config/rs6000/option-defaults.h +++ b/gcc/config/rs6000/option-defaults.h @@ -39,11 +39,11 @@ #endif #if TARGET_DEFAULT & OPTION_MASK_64BIT -#define OPT_ARCH64 "!"OPT_32 +#define OPT_ARCH64 "!" OPT_32 #define OPT_ARCH32 OPT_32 #else #define OPT_ARCH64 OPT_64 -#define OPT_ARCH32 "!"OPT_64 +#define OPT_ARCH32 "!" OPT_64 #endif /* Support for a compile-time default CPU, et cetera. The rules are: diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c5909db2f03..1f01f8e4d46 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1025,12 +1025,30 @@ (const_int 0)))] "") +;; PPE42 does not support lbzux instruction +(define_insn "" + [(set (match_operand:HI 0 "gpc_reg_operand" "=r") + (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m")))] + "(rs6000_cpu == PROCESSOR_PPE42) && + update_indexed_address_mem (operands[1], VOIDmode)" + "* +{ + { + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[1],0),0)); + sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1); + return buf; + } +}" + [(set_attr "type" "load_ux") + (set_attr "length" "8")]) + (define_insn "" [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] "" "@ - lbz%U1%X1 %0,%1 #DEBUGME 2 %1 + lbz%U1%X1 %0,%1 rlwinm %0,%1,0,0xff" [(set_attr_alternative "type" [(if_then_else @@ -1159,6 +1177,24 @@ "" "") +;; PPE42 does not support lhzux instruction +(define_insn "" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m")))] + "(rs6000_cpu == PROCESSOR_PPE42) && + update_indexed_address_mem (operands[1], VOIDmode)" + "* +{ + { + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[1],0),0)); + sprintf(buf,\"add %d,%%1 #lhzux\;lhz %%0,0(%d)\",r1,r1); + return buf; + } +}" + [(set_attr "type" "load_ux") + (set_attr "length" "8")]) + (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] @@ -2310,7 +2346,7 @@ ;; [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ;; (zero_extend:SI ;; (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] -;; "" +;; "rs6000_cpu != PROCESSOR_PPE42" ;; "lhbrx %0,%y1" ;; [(set_attr "length" "4") ;; (set_attr "type" "load")]) @@ -2331,7 +2367,7 @@ ;; (bswap:HI ;; (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r"))) ;; (clobber (match_scratch:SI 2 "=X,X,&r"))] -;; "" +;; "rs6000_cpu != PROCESSOR_PPE42" ;; "@ ;; lhbrx %0,%y1 ;; sthbrx %1,%y0 @@ -2386,7 +2422,7 @@ ;; [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r") ;; (bswap:SI ;; (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))] -;; "" +;; "rs6000_cpu != PROCESSOR_PPE42" ;; "@ ;; lwbrx %0,%y1 ;; stwbrx %1,%y0 @@ -9116,6 +9152,45 @@ (const_int 0)))] "") +;; ppe42 does not support lhzux instruction +(define_insn "*movhi_internal_load" + [(set (match_operand:HI 0 "nonimmediate_operand" "=r") + (match_operand:HI 1 "input_operand" "m"))] + "rs6000_cpu == PROCESSOR_PPE42 && + gpc_reg_operand (operands[0], HImode) && + update_indexed_address_mem (operands[1], VOIDmode)" + "* +{ + { + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[1],0),0)); + sprintf(buf,\"add %d,%%1 #lhzux\;lhz %%0,0(%d)\",r1,r1); + return buf; + } +}" + [(set_attr "type" "load_ux") + (set_attr "length" "8")]) + +;; ppe42 does not support sthux instruction +(define_insn "*movhi_internal_store" + [(set (match_operand:HI 0 "nonimmediate_operand" "=m") + (match_operand:HI 1 "input_operand" "r"))] + "rs6000_cpu == PROCESSOR_PPE42 && + gpc_reg_operand (operands[1], HImode) && + update_indexed_address_mem (operands[0], VOIDmode)" + "* +{ + { + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[0],0),0)); + sprintf(buf,\"add %d,%%0 #sthux\;sth %%1,0(%d)\",r1,r1); + return buf; + } +}" + [(set_attr "type" "store_ux") + (set_attr "length" "8")]) + + (define_insn "*movhi_internal" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h") (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))] @@ -9156,6 +9231,45 @@ "" "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") +;; ppe42 does not support lbzux +(define_insn "*movqi_internal_1oad" + [(set (match_operand:QI 0 "nonimmediate_operand" "=r") + (match_operand:QI 1 "input_operand" "m"))] + "(rs6000_cpu == PROCESSOR_PPE42) && + gpc_reg_operand (operands[0], QImode) && + update_indexed_address_mem (operands[1], VOIDmode)" + "* +{ + { + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[1],0),0)); + sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1); + return buf; + } +}" + [(set_attr "type" "load_ux") + (set_attr "length" "8")]) + +;; ppe42 does not support stbux +(define_insn "*movqi_internal_store" + [(set (match_operand:QI 0 "nonimmediate_operand" "=m") + (match_operand:QI 1 "input_operand" "r"))] + "(rs6000_cpu == PROCESSOR_PPE42) && + gpc_reg_operand (operands[1], QImode) && + update_indexed_address_mem (operands[0], VOIDmode)" + "* +{ + { + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[0],0),0)); + sprintf(buf,\"add %d,%%0 #stbux\;stb %%1,0(%d)\",r1,r1); + return buf; + } +}" + [(set_attr "type" "store_ux") + (set_attr "length" "8")]) + + (define_insn "*movqi_internal" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h") (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))] @@ -9163,7 +9277,7 @@ || gpc_reg_operand (operands[1], QImode)" "@ mr %0,%1 - lbz%U1%X1 %0,%1 #DEBUGME 3 %1 + lbz%U1%X1 %0,%1 stb%U0%X0 %1,%0 li %0,%1 mf%1 %0 diff --git a/gcc/cp/cfns.gperf b/gcc/cp/cfns.gperf index 05ca753927e..3a85aaa936f 100644 --- a/gcc/cp/cfns.gperf +++ b/gcc/cp/cfns.gperf @@ -21,7 +21,7 @@ __inline #endif static unsigned int hash (const char *, unsigned int); #ifdef __GNUC__ -__inline +//__inline #endif const char * libc_name_p (const char *, unsigned int); %} diff --git a/gcc/cp/cfns.h b/gcc/cp/cfns.h index c845ddf08ea..dca250ef555 100644 --- a/gcc/cp/cfns.h +++ b/gcc/cp/cfns.h @@ -52,7 +52,7 @@ __inline #endif static unsigned int hash (const char *, unsigned int); #ifdef __GNUC__ -__inline +//__inline #endif const char * libc_name_p (const char *, unsigned int); /* maximum key range = 391, duplicates = 0 */ |