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| author | Patrick Williams <patrick@stwcx.xyz> | 2016-10-29 12:37:55 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-10-29 12:37:55 -0500 |
| commit | d8a1bac8634033a3edd4e9a22455f97318718f43 (patch) | |
| tree | 4ad119147e22d25e2e431828d484fd2eaf5130df | |
| parent | 14ca4616e0ba055c30ad36144c44db8a6f09f6ff (diff) | |
| parent | 72beec1539befc791ffe217f1084ee9eab7df4e5 (diff) | |
| download | ppe42-gcc-d8a1bac8634033a3edd4e9a22455f97318718f43.tar.gz ppe42-gcc-d8a1bac8634033a3edd4e9a22455f97318718f43.zip | |
Merge pull request #2 from dgilbert999/gcc-4_9_2-ppe42
Fix insn attribute length field for load zero-extend operation
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 4 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 47 |
2 files changed, 22 insertions, 29 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 90f4a34b59f..3ee85aaf9e1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -19197,7 +19197,7 @@ rs6000_emit_cbranch (enum machine_mode mode, rtx operands[]) char * output_fused_cbranch (rtx operands[], const char *label, rtx insn) { - static char string[32]; + static char string[64]; enum rtx_code code = GET_CODE (operands[1]); int need_longbranch = get_attr_length (insn) == 8; char *s = string; @@ -19273,7 +19273,7 @@ output_fused_cbranch (rtx operands[], const char *label, rtx insn) char * output_fused_bnbwi(rtx operands[], const char *label, bool longbranch) { - static char string[32]; + static char string[64]; enum rtx_code code = GET_CODE (operands[1]); int regno = REGNO(operands[2]); int bitpos = INTVAL(operands[3]); //31 - exact_log2(INTVAL(operands[3])); diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 355a507780a..c5909db2f03 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -877,40 +877,33 @@ "" "") -(define_insn "" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] - "" - " - rlwinm %0,%1,0,0xff" - [(set_attr_alternative "type" - [(if_then_else - (match_test "update_indexed_address_mem (operands[1], VOIDmode)") - (const_string "load_ux") - (if_then_else - (match_test "update_address_mem (operands[1], VOIDmode)") - (const_string "load_u") - (const_string "*")))])]) - -;; FIXME this insn has a length problem - needs to be split -;; one when two instructions are used the set_addr "length" "8" +;; Catch the lbzux case for PPE42 as it does not support lbzux instruction +;; lbzux RT, RA,RB RT is operand[0] RA,RB is operand[1] +;; replace with add RA,RA,RB;; lbz RT, 0(RA) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m")))] - "" + "(rs6000_cpu == PROCESSOR_PPE42) && + update_indexed_address_mem (operands[1], VOIDmode)" "* { - /* PPE42 does not support the lbzux instruction */ - /* Probably a better way to implement this */ - if(update_indexed_address_mem (operands[1], VOIDmode)) { - static char buf[16]; - int r1 = REGNO(XEXP(XEXP(operands[1],0),0)); - sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1); - return buf; + static char buf[40]; + int r1 = REGNO(XEXP(XEXP(operands[1],0),0)); + sprintf(buf,\"add %d,%%1 #lbzux\;lbz %%0,0(%d)\",r1,r1); + return buf; } - else return \"lbz%U1%X1 %0,%1\"; }" + [(set_attr "type" "load_ux") + (set_attr "length" "8")]) + +(define_insn "" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] + "" + "@ + lbz%U1%X1 %0,%1 + rlwinm %0,%1,0,0xff" [(set_attr_alternative "type" [(if_then_else (match_test "update_indexed_address_mem (operands[1], VOIDmode)") @@ -919,7 +912,7 @@ (match_test "update_address_mem (operands[1], VOIDmode)") (const_string "load_u") (const_string "load"))) - ])]) + (const_string "*")])]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
