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authorrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2011-01-11 18:28:59 +0000
committerrth <rth@138bc75d-0d04-0410-961f-82ee72b054a4>2011-01-11 18:28:59 +0000
commit2225047a0d9c2d65aadd46b4c4ba2f9764564bbb (patch)
tree7deed119e939b6f57b15932b9e0d854c7e425658
parent8af291b5dc3ef8cdfc1a805f5907f64f6f2bfef5 (diff)
downloadppe42-gcc-2225047a0d9c2d65aadd46b4c4ba2f9764564bbb.tar.gz
ppe42-gcc-2225047a0d9c2d65aadd46b4c4ba2f9764564bbb.zip
mn10300: Define the A and D constraints.
This will allow combining am33 and mn103 alternatives without having to resort to the enabled attribute. The existing 'A' constraint renamed to 'c'. Thankfully this existing accumulator constraint doesn't appear in either newlib or eglibc sources. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@168675 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/mn10300/constraints.md11
-rw-r--r--gcc/config/mn10300/mn10300.md8
3 files changed, 19 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8d5fb422d77..5b290b788cf 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2011-01-11 Richard Henderson <rth@redhat.com>
+ * config/mn10300/constraints.md ("c"): Rename from "A".
+ ("A", "D"): New constraint letters.
+ * config/mn10300/mn10300.md (fmasf4): Use the "c" constraint.
+ (fmssf4, fnmasf4, fnmssf4): Likewise.
+
* config/mn10300/mn10300.md (isa): New attribute.
(enabled): New attribute.
diff --git a/gcc/config/mn10300/constraints.md b/gcc/config/mn10300/constraints.md
index 509970cd4b6..c9863fc508c 100644
--- a/gcc/config/mn10300/constraints.md
+++ b/gcc/config/mn10300/constraints.md
@@ -23,6 +23,15 @@
(define_register_constraint "a" "ADDRESS_REGS"
"An address register.")
+;; This can be used for QI/HImode memory operations, and most arithmetic.
+;; AM33 supports these on all registers, where MN103 needs DATA_REGS.
+(define_register_constraint "D" "TARGET_AM33 ? GENERAL_REGS : DATA_REGS"
+ "A general register for AM33, and a data register otherwise.")
+
+;; Similarly for ADDRESS_REGS vs GENERAL_REGS.
+(define_register_constraint "A" "TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS"
+ "A general register for AM33, and an address register otherwise.")
+
(define_register_constraint "y" "SP_REGS"
"An SP register (if available).")
@@ -32,7 +41,7 @@
(define_register_constraint "f" "TARGET_AM33_2 ? FP_REGS : NO_REGS"
"A floating point register.")
-(define_register_constraint "A" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS"
+(define_register_constraint "c" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS"
"A floating point accumulator register.")
(define_memory_constraint "Q"
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index bfa453f17c0..1773a03624b 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -2717,7 +2717,7 @@
)
(define_insn "fmasf4"
- [(set (match_operand:SF 0 "register_operand" "=A")
+ [(set (match_operand:SF 0 "register_operand" "=c")
(fma:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f")))
@@ -2730,7 +2730,7 @@
)
(define_insn "fmssf4"
- [(set (match_operand:SF 0 "register_operand" "=A")
+ [(set (match_operand:SF 0 "register_operand" "=c")
(fma:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")
(neg:SF (match_operand:SF 3 "register_operand" "f"))))
@@ -2743,7 +2743,7 @@
)
(define_insn "fnmasf4"
- [(set (match_operand:SF 0 "register_operand" "=A")
+ [(set (match_operand:SF 0 "register_operand" "=c")
(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
(match_operand:SF 2 "register_operand" "f")
(match_operand:SF 3 "register_operand" "f")))
@@ -2756,7 +2756,7 @@
)
(define_insn "fnmssf4"
- [(set (match_operand:SF 0 "register_operand" "=A")
+ [(set (match_operand:SF 0 "register_operand" "=c")
(fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
(match_operand:SF 2 "register_operand" "f")
(neg:SF (match_operand:SF 3 "register_operand" "f"))))
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