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* imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQPPeng Fan2016-05-241-2/+2
| | | | | | | | Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we will get wrong speed grade info i.MX6DQP. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: use simpler runtime cpu dection macrosPeng Fan2016-05-241-7/+6
| | | | | | | | Use simpler runtime cpu dection macros. i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: correct speed grading info for i.MX6ULPeng Fan2016-05-181-0/+15
| | | | | | | Correct speed grading info for i.MX6UL Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ul configure the PMIC_STBY_REQ pin as open drainPeng Fan2016-03-251-1/+11
| | | | | | | | | Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin for i.MX 6UltraLite TO1.0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6ul: skip setting ahb ratePeng Fan2016-03-251-7/+12
| | | | | | | | To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx6: Fix incorrect clear mmdc_ch0 handshake maskYe Li2016-03-251-1/+4
| | | | | | | | | | | Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: hdmi: handle overflow conditionPeng Fan2016-03-141-1/+12
| | | | | | | | | | | | If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to do TMDS software reset and write to clear fc_invidconf register. We need minimum 3 times to write to clear the fc_invidconf register, so choose 5 loops here. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Sandor Yu <sandor.yu@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* imx: mx6: implement functions to boot auxiliary corePeng Fan2016-02-211-0/+38
| | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx: mx6: Implement mmc_get_env_partSoeren Moch2016-02-211-3/+33
| | | | | | | | | | commit 216d286c7e3d3d83d4d8ccaf0415192e1b1040c0 [imx: mx6: implement mmc_get_env_dev] introduced selection of the environment device according to the boot device when booting from SD/MMC. Extend this functionality for also selecting the device partition. Signed-off-by: Soeren Moch <smoch@web.de>
* imx: mx6: implement mmc_get_env_devPeng Fan2016-02-041-0/+32
| | | | | | | | | | Implement mmc_get_env_dev, devno can be got from smbr1 of SRC. Introduce a weak function board_mmc_get_env_dev, different boards can implement it according to different sdhc controllers that used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* mx6: soc: Add ENET2 mac address supportYe Li2016-02-021-9/+23
| | | | | | | The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading MAC address from fuse for ENET2. Signed-off-by: Ye Li <ye.li@nxp.com>
* imx: mx6: implement reset_miscPeng Fan2015-11-121-0/+7
| | | | | | | | We need to power down lcdif before uboot reset to make reset can pass stress test. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* arm: imx: add secure boot fuse details for imx6 SoCAdrian Alonso2015-10-301-0/+8
| | | | | | | Add secure boot fuse details (location) bank = 0, word = 6; for imx6 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* arm: imx-common: init: rework wdog settings for imx6/imx7Adrian Alonso2015-09-131-14/+0
| | | | | | Rework imx_set_wdog_powerdown to be reused by imx6 and imx7 Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* arm: imx: imx-common: init: move arch init common setupAdrian Alonso2015-09-131-87/+0
| | | | | | | | Move common imx6 arch init setup, init.c can be extended and reused to support imx7 SoC keeping init arch common code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* arm: imx: common rework cache settings for imx6Adrian Alonso2015-09-131-95/+0
| | | | | | | Rework cache settings for imx6, move cache configuration to imx-common/cache.c so it can be reused for newer SoC Signed-off-by: Adrian Alonso <aalonso@freescale.com>
* thermal: imx_thermal: rework driver to be reusedAdrian Alonso2015-09-131-1/+1
| | | | | | | | Rework imx_thermal driver to be used across i.MX processor that support thermal sensor Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul update soc related settingsPeng Fan2015-08-021-5/+4
| | | | | | | | 1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-021-1/+4
| | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-021-2/+9
| | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6 correct get_cpu_revPeng Fan2015-06-271-1/+3
| | | | | | | | | | | The DIGPROG register map: 23 ------- 16 | 15 ------ 8 | 7 --- 0 | Major upper | Major Lower | Minor | We also need to account for Major Lower. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-191-0/+38
| | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-191-0/+41
| | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* mx6: Set shared override bit in PL310 AUX_CTRL registerFabio Estevam2015-05-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* mx6: soc: Switch to cold resetDirk Behme2015-03-131-0/+18
| | | | | | | | Disable the warm reset and enable the cold reset for a more reliable restart ('reset'). This is taken from the Linux kernel, see imx_src_init() in arch/arm/mach-imx/src.c. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
* imx:mx6 remove duplicated includesPeng Fan2015-03-131-1/+0
| | | | | | There is no need to include asm/bootm.h twice, so remove one. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ARM: imx6 Add WDOG3 for i.MX6SXPeng Fan2015-02-171-0/+5
| | | | | | | There are three wdogs for i.MX 6SoloX. Add wdog3 support in function imx_set_wdog_powerdown. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ARM: imx6: disable bandgap self-bias after bootPeng Fan2015-02-171-0/+24
| | | | | | | | | | | The self-bias circuit is used by the bandgap during startup. Once the bandgap has stabilized, the self-bias circuit should be disabled for best noise performance of analog blocks. Also this bit should be disabled before the chip enters STOP mode or when ever the regular bandgap is disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* imx: mx6: Fixed AIPS3 base address issueYe.Li2015-02-101-1/+1
| | | | | | | | | Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem. Signed-off-by: Ye.Li <B37916@freescale.com>
* mx6: thermal: Check cpu temperature via thermal sensorYe.Li2014-11-211-0/+15
| | | | | | | | Add imx6 thermal device to mx6 soc file. Read the cpu temperature using this device to access onchip thermal sensor. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* arm: imx: make bmode command work with SPL/U-Boot comboNikita Kiryanov2014-11-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The bmode command forces the SoC to use a specific boot device by writing its boot mode into SRC_GPR9, and notifying the SoC of the change using SRC_GPR10[28] bit: if the bit is on, bootROM uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine the boot device. SPL on the other hand is oblivious to this distinction, so once the bootROM loads SPL from the device configured in SRC_GPR10, SPL will attempt to load U-Boot from the device configured in SRC_SMBR1, which is not updated by the bootROM to the value in SRC_GPR9. The result is that the selected boot device is not used across all the boot stages. Update spl_boot_device() to look at gpr9 when necessary. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-051-0/+17
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| * imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-11-031-0/+17
| | | | | | | | | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2014-10-271-0/+1
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| * ARM: i.MX6: include prototype for get_board_rev()Eric Nelson2014-10-211-0/+1
| | | | | | | | | | | | | | Include <asm/bootm.h> to see the prototype for get_board_rev() and prevent warning "Should it be static?" with "make C=1". Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | imx: add missing includesJeroen Hofstee2014-10-251-0/+1
|/ | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD resetYe.Li2014-09-291-8/+16
| | | | | | | | | Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Customers may set this in DDR script or use BT_FREQ to select low freq boot. Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: Support i.MX6 High Assurance Boot authenticationNitin Garg2014-09-221-0/+15
| | | | | | | | | | | | When CONFIG_SECURE_BOOT is enabled, the signed images like kernel and dtb can be authenticated using iMX6 CAAM. The added command hab_auth_img can be used for HAB authentication of images. The command takes the image DDR location, IVT (Image Vector Table) offset inside image as parameters. Detailed info about signing images can be found in Freescale AppNote AN4581. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
* mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov2014-09-091-4/+4
| | | | | | Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* iMX6: Disable the L2 before chaning the PL310 latencyYe.Li2014-09-091-0/+3
| | | | | | | | | | | The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
* mx6: add support of multi-processor commandGabriel Huau2014-08-201-0/+6
| | | | | | | | | This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: soc: Do not apply the PFD erratum for mx6soloxFabio Estevam2014-07-231-0/+4
| | | | | | The PFD issue is not present on mx6solox, so skip it in this case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Add support for the mx6solox variantFabio Estevam2014-07-101-0/+26
| | | | | | | | | | | | mx6solox is the newest member of the mx6 family. Some of the new features on this variants are: - Cortex M4 microcontroller (besides the CortexA9) - Dual Gigabit Ethernet Add the initial support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Update the comments of set_ldo_voltage()Fabio Estevam2014-07-091-3/+2
| | | | | | | | | | | | | Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces set_ldo_voltage() function that can be used to set the voltages of any of the three LDO regulators controlled by the PMU_REG_CORE register. Prior to this commit there was a single set_vddsoc() which only configured the VDDSOC regulator. Update the comments to align with the new set_ldo_voltage() implementation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: Enable L2 cache supportFabio Estevam2014-02-111-0/+58
| | | | | | | | | | | Add L2 cache support and enable it by default. Configure the L2 cache in the same way as done by FSL kernel: http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mx6: Distinguish mx6dual from mx6quadFabio Estevam2014-02-111-3/+11
| | | | | | | | | | | | Currently when we boot a mx6dual U-boot reports that it is a mx6quad. Report it as MX6D instead: CPU: Freescale i.MX6D rev1.2 at 792 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
* imx6: make sure MMDC_CHx_MASK is clear to avoid warm reset failureAnson Huang2014-02-111-0/+11
| | | | | | | | | Boot ROM may mask MMDC_CHx_MASK in CCM_CCDR(such as i.MX6SL TO1.2), it will cause warm reset fail, need to clear this MMDC_CHx_MASK field to make sure all the i.MX6 series SOCs reset function work. Otherwise, uboot "reset" command will fail, tested on i.MX6SL EVK board with TO1.2. Signed-off-by: Anson Huang <b20788@freescale.com>
* imx6: ensure AHB clock is 132MHz in low freq boot modeAnson Huang2014-02-111-0/+20
| | | | | | | | | | | | For low freq boot mode(ARM boot up with 396MHz), ROM will not set AHB clock to 132MHz, and the reset value of AHB divider is incorrect which will lead to wrong AHB rate, need to correct it. To enable low freq boot mode, need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL SabreSD board and i.MX6SL EVK board. Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Anson Huang <b20788@freescale.com>
* mx6: Revert "mx6: soc: Disable VDDPU regulator"Fabio Estevam2014-01-171-41/+0
| | | | | | | | | Commit 022298278 (mx6: soc: Disable VDDPU regulator) is causing kernel hang for people using FSL kernel 3.0.35 and 3.10, so revert it for now. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Reported-by: Pierre Aubert <p.aubert@staubli.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6: soc: Disable VDDPU regulatorFabio Estevam2014-01-021-0/+41
| | | | | | | | | As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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