diff options
| author | Ye Li <ye.li@nxp.com> | 2016-03-09 16:13:48 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-03-25 13:55:54 +0100 |
| commit | b777789ebd193587a8e4700dce656523df821370 (patch) | |
| tree | 9afc5474db13a66b5d16e9a612db7a6f666038e9 /arch/arm/cpu/armv7/mx6/soc.c | |
| parent | 312a6c016a2d81aa3fbc605f5c0c315b6a4e3464 (diff) | |
| download | blackbird-obmc-uboot-b777789ebd193587a8e4700dce656523df821370.tar.gz blackbird-obmc-uboot-b777789ebd193587a8e4700dce656523df821370.zip | |
imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 91a3debe91..bdd41b07f4 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); + else + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); writel(reg, &mxc_ccm->ccdr); } |
