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path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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* Remove indirection of vector<T*> in favor of deque<T>David Blaikie2014-11-291-55/+52
| | | | llvm-svn: 222958
* Use deque<T> rather than vector<T*> since it provides the same invalidation ↵David Blaikie2014-11-291-16/+14
| | | | | | | | | | | | | | | semantics (at least when removal is not needed) without the extra indirection/ownership complexity Order matters for this container, it seems (using a forward_list and replacing the original push_backs with emplace_fronts caused test failures). I didn't look too deeply into why. (& in retrospect, I might go back & change some of the forward_lists I introduced to deques anyway - since most don't require removal, deque is a more memory-friendly data structure (moderate locality while not invalidating pointers)) llvm-svn: 222950
* Constify some things in preparation for CodeGenSubRegIndex to be stored by ↵David Blaikie2014-11-291-53/+52
| | | | | | value in their container, removing the indirection llvm-svn: 222949
* Reduce size of some tables in tablegen register info output.Craig Topper2014-11-221-50/+49
| | | | | | Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k. llvm-svn: 222621
* Add extra new line and remove some trailing whitespace from tablegen ↵Craig Topper2014-11-211-5/+5
| | | | | | RegisterInfo output file. llvm-svn: 222508
* Remove unnecessary extra spaces from tablegen register info output.Craig Topper2014-11-201-1/+1
| | | | llvm-svn: 222411
* Use array_lengthof instead of sizeof(array)/sizeof(element) in a tablegen ↵Craig Topper2014-11-201-5/+4
| | | | | | output. llvm-svn: 222410
* Move register class name strings to a single array in MCRegisterInfo to ↵Craig Topper2014-11-171-2/+14
| | | | | | | | reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-301-5/+5
| | | | llvm-svn: 207611
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-3/+3
| | | | llvm-svn: 205610
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-14/+15
| | | | | | class. llvm-svn: 203378
* Fix indentation.Craig Topper2014-02-271-1/+1
| | | | llvm-svn: 202344
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-1/+1
| | | | llvm-svn: 190770
* llvm-tblgen: Stabilize subreg index tables.Benjamin Kramer2013-09-111-2/+2
| | | | | | Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic. llvm-svn: 190514
* Add an OtherPreserved field to the CalleeSaved TableGen class.Jakob Stoklund Olesen2013-08-231-1/+13
| | | | | | | | | | This field specifies registers that are preserved across function calls, but that should not be included in the generates SaveList array. This can be used ot generate regmasks for architectures that save registers through other means, like SPARC's register windows. llvm-svn: 189084
* Using a different loop induction variable than the enclosing scope. No ↵Aaron Ballman2013-07-251-2/+2
| | | | | | functional changes intended. llvm-svn: 187159
* RegPressure: Order the "pressure sets" by number of regunits per set.Andrew Trick2013-07-251-6/+12
| | | | | | This lets heuristics easily pick the most important set to follow. llvm-svn: 187108
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 llvm-svn: 185094
* Remove unimplemented definition. Found using [-Wunused-member-function].Jakub Staszak2013-06-061-2/+0
| | | | llvm-svn: 183426
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-2/+2
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-311-2/+18
| | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-281-14/+3
| | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 llvm-svn: 182783
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-161-1/+3
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-171-1/+1
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-5/+5
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. llvm-svn: 170610
* RegisterPresssureTracker: Track live physical register by unit.Andrew Trick2012-12-051-2/+6
| | | | | | | | This is much simpler to reason about, more efficient, and fixes some corner cases involving implicit super-register defs. Fixed rdar://12797931. llvm-svn: 169425
* RegisterPressure API. Add support for physical register units.Andrew Trick2012-12-051-10/+70
| | | | | | | | | | | | | At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. llvm-svn: 169360
* Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen2012-11-291-7/+7
| | | | | | Use this type for arrays of physical registers. llvm-svn: 168850
* Generate a table-driven version of TRI::composeSubRegIndices().Jakob Stoklund Olesen2012-11-011-26/+102
| | | | | | | | | | Explicitly allow composition of null sub-register indices, and handle that common case in an inlinable stub. Use a compressed table implementation instead of the previous nested switches which generated pretty bad code. llvm-svn: 167190
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-1/+1
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-101-1/+1
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-2/+2
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-7/+7
| | | | llvm-svn: 163999
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-4/+12
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Clean the sub-reg index composition maps at emission.Jakob Stoklund Olesen2012-09-111-2/+2
| | | | | | | Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. llvm-svn: 163629
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-111-2/+2
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. llvm-svn: 163628
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-151-13/+2
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. llvm-svn: 161964
* Eliminate the large XXXSubRegTable constant arrays.Jakob Stoklund Olesen2012-07-271-53/+31
| | | | | | | | | | | These tables were indexed by [register][subreg index] which made them, very large and sparse. Replace them with lists of sub-register indexes that match the existing lists of sub-registers. MCRI::getSubReg() becomes a very short linear search, like getSubRegIndex() already was. llvm-svn: 160843
* Differentially encode all MC register lists.Jakob Stoklund Olesen2012-07-251-44/+30
| | | | | | | This simplifies MCRegisterInfo and shrinks the target descriptions a bit more. llvm-svn: 160758
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-9/+54
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Didn't mean to export this function.Jakob Stoklund Olesen2012-05-311-0/+1
| | | | llvm-svn: 157756
* Emit register unit root tables.Jakob Stoklund Olesen2012-05-311-0/+17
| | | | | | | | | | Each register unit has one or two root registers. The full set of registers containing a given register unit can be computed as the union of the root registers and their super-registers. Provide an MCRegUnitRootIterator class to enumerate the roots. llvm-svn: 157753
* Print uint16_t numbers without a sign.Jakob Stoklund Olesen2012-05-301-1/+1
| | | | | | It seems I broke C++11. llvm-svn: 157711
* Emit register unit lists for each register.Jakob Stoklund Olesen2012-05-291-3/+75
| | | | | | | | | | | | | | | | Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. llvm-svn: 157650
* Compress MCRegisterInfo register name tables.Jakob Stoklund Olesen2012-05-251-3/+16
| | | | | | | Store (debugging) register names as offsets into a string table instead of as char pointers. llvm-svn: 157449
* Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen2012-05-161-3/+2
| | | | | | | | | | | TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. llvm-svn: 156960
* TableGen'erate mapping physical registers to encoding values.Jim Grosbach2012-05-151-4/+26
| | | | | | | | | | | Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. llvm-svn: 156829
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-041-51/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-34/+1
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen2012-05-031-4/+4
| | | | | | | | This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. llvm-svn: 156121
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