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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-05-16 18:03:08 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-05-16 18:03:08 +0000 |
| commit | 9ae96c7aab27b88d44221c7de30305fcafb78024 (patch) | |
| tree | bdb436593ac9c7785054551732e5507281fec53e /llvm/utils/TableGen/RegisterInfoEmitter.cpp | |
| parent | d819aa5c54a5036c995c7024d709d42998db601b (diff) | |
| download | bcm5719-llvm-9ae96c7aab27b88d44221c7de30305fcafb78024.tar.gz bcm5719-llvm-9ae96c7aab27b88d44221c7de30305fcafb78024.zip | |
Add TargetRegisterInfo::getCoveringLanes().
This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().
llvm-svn: 182034
Diffstat (limited to 'llvm/utils/TableGen/RegisterInfoEmitter.cpp')
| -rw-r--r-- | llvm/utils/TableGen/RegisterInfoEmitter.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 1b5d90b8bda..f519b21de06 100644 --- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -1270,7 +1270,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" - << " SubRegIndexNameTable, SubRegIndexLaneMaskTable) {\n" + << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x"; + OS.write_hex(RegBank.CoveringLanes); + OS << ") {\n" << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size()+1 << ", RA, PC,\n " << TargetName << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" |
