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path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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* [Sparc] Use target name instead of namespace as prefix for MCRegisterClasses ↵Jacob Baungard Hansen2016-11-211-1/+1
| | | | | | | | | | | | | | | | | | | array Summary: For Sparc the namespace (SP) is different from the target name (Sparc), which causes the name of the array in this declaration to differ from the name used in the definition. Patch by Daniel Cederman. Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: https://reviews.llvm.org/D23650 llvm-svn: 287528
* [tablegen] Merge duplicate definitions of getMinimalTypeForRange. NFC.Daniel Sanders2016-11-191-16/+9
| | | | | | | | | | | | Summary: Depends on D25614 Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25617 llvm-svn: 287438
* Avoid some copies by using const references.Benjamin Kramer2016-05-271-1/+1
| | | | | | | clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
* Fix Clang-tidy modernize-use-bool-literals in generated Target code; other ↵Eugene Zelenko2016-05-171-26/+43
| | | | | | | | | | | | minor fixes; other minor fixes. Make generated code more readable. Fix some Include What You Use warnings. Differential revision: http://reviews.llvm.org/D20317 llvm-svn: 269783
* TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun2016-04-281-1/+3
| | | | | | This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
* TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()Matthias Braun2016-04-281-12/+29
| | | | | | | | | This function performs the reverse computation of composeSubRegIndexLaneMask(). It will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267849
* Remove extra 'nullptr' entry from an array in tablegen register info file. ↵Craig Topper2015-09-221-1/+1
| | | | | | It should never have been accessed. llvm-svn: 248246
* Fix formatting of a tablegen register info file by putting a line break in a ↵Craig Topper2015-09-221-3/+2
| | | | | | better place. llvm-svn: 248245
* Use makeArrayRef and None to simplify some code in a tablegen register info ↵Craig Topper2015-09-221-12/+18
| | | | | | | | | | file. Additionally const correct a couple static array. Previously the code added an extra nullptr entry to a static array and then created an ArrayRef with a size one less than the static array. If there were no other entries the array would just contain the nullptr and the ArrayRef would be crated with size 0. Instead, put the right number of entries in the array and explicitly emit 'None' if the size would be 0. This allows the static array constructor of makeArrayRef to be used. llvm-svn: 248244
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-101-0/+12
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* MIR Serialization: Serialize the register mask machine operands.Alex Lorenz2015-06-291-0/+22
| | | | | | | | | | | | | | | | | This commit implements serialization of the register mask machine operands. This commit serializes only the call preserved register masks that are defined by a target, it doesn't serialize arbitrary register masks. This commit also extends the TargetRegisterInfo class and TableGen so that the users of TRI can get the list of all the call preserved register masks and their names. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10673 llvm-svn: 240966
* TableGen: Generate more const goodnessMatthias Braun2015-04-011-2/+2
| | | | llvm-svn: 233857
* RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun2015-03-311-0/+1
| | | | | | | | | | Specify an allocation order with a register class. This is used by register allocators with a greedy heuristic. This is usefull as it is sometimes beneficial to color more constrained classes first. Differential Revision: http://reviews.llvm.org/D8626 llvm-svn: 233743
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-191-1/+3
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-111-2/+3
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* TblGen: Remove copy of SmallVector::operator==. NFC intended.Benjamin Kramer2015-03-021-10/+1
| | | | llvm-svn: 230964
* Switch a std::map to a DenseMap in CodeGenRegisters.Owen Anderson2015-02-271-7/+9
| | | | | | | | The keys of the map are unique by pointer address, so there's no need to use the llvm::less comparator. This allows us to use DenseMap instead, which reduces tblgen time by 20% on my stress test. llvm-svn: 230769
* STLExtras: Provide less/equal functors with templated function call ↵David Blaikie2015-02-021-2/+2
| | | | | | | | | | | | | | | | operators, plus a deref'ing functor template utility Similar to the C++14 void specializations of these templates, useful as a stop-gap until LLVM switches to '14. Example use-cases in tblgen because I saw some functors that looked like they could be simplified/refactored. Reviewers: dexonsmith Differential Revision: http://reviews.llvm.org/D7324 llvm-svn: 227828
* Replace another std::set in the core of CodeGenRegister, this time with ↵Owen Anderson2015-01-311-1/+1
| | | | | | | | sorted arrays. The hot path through this region of code does lots of batch inserts into sets. By storing them as sorted arrays, we can defer the sorting to the end of the batch, which is dramatically more efficient. This reduces tblgen runtime by 25% on my worst-case target. llvm-svn: 227682
* Change more of the guts of CodeGenRegister's RegUnit tracking to be based on ↵Owen Anderson2015-01-311-8/+8
| | | | | | | | bit vectors. This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case. llvm-svn: 227678
* Tablegen'erate lanemasks for register units.Matthias Braun2014-12-101-6/+35
| | | | | | Now we can relate lanemasks in a virtual register to register units. llvm-svn: 223889
* Add function that translates subregister lane masks to other subregs.Matthias Braun2014-12-101-1/+96
| | | | | | | This works like the composeSubRegisterIndices() function but transforms a subregister lane mask instead of a subregister index. llvm-svn: 223874
* Let tablegen compute maximum lanemask for regs/regclasses.Matthias Braun2014-12-101-1/+2
| | | | | | | | Let tablegen compute the combination of subregister lanemasks for all subregisters in a register/register class. This is preparation for further work subregister allocation llvm-svn: 223873
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-30/+19
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-47/+43
| | | | | | range-for isn't suitable. llvm-svn: 223260
* Remove indirection of vector<T*> in favor of deque<T>David Blaikie2014-11-291-55/+52
| | | | llvm-svn: 222958
* Use deque<T> rather than vector<T*> since it provides the same invalidation ↵David Blaikie2014-11-291-16/+14
| | | | | | | | | | | | | | | semantics (at least when removal is not needed) without the extra indirection/ownership complexity Order matters for this container, it seems (using a forward_list and replacing the original push_backs with emplace_fronts caused test failures). I didn't look too deeply into why. (& in retrospect, I might go back & change some of the forward_lists I introduced to deques anyway - since most don't require removal, deque is a more memory-friendly data structure (moderate locality while not invalidating pointers)) llvm-svn: 222950
* Constify some things in preparation for CodeGenSubRegIndex to be stored by ↵David Blaikie2014-11-291-53/+52
| | | | | | value in their container, removing the indirection llvm-svn: 222949
* Reduce size of some tables in tablegen register info output.Craig Topper2014-11-221-50/+49
| | | | | | Primarily done by using SequenceToOffsetTable to reduce the register pressure set tables and then sizing the indices into the tables appropriately. Size a few other table entries based on content as well. Reduces X86RegisterInfo.o by ~9k. llvm-svn: 222621
* Add extra new line and remove some trailing whitespace from tablegen ↵Craig Topper2014-11-211-5/+5
| | | | | | RegisterInfo output file. llvm-svn: 222508
* Remove unnecessary extra spaces from tablegen register info output.Craig Topper2014-11-201-1/+1
| | | | llvm-svn: 222411
* Use array_lengthof instead of sizeof(array)/sizeof(element) in a tablegen ↵Craig Topper2014-11-201-5/+4
| | | | | | output. llvm-svn: 222410
* Move register class name strings to a single array in MCRegisterInfo to ↵Craig Topper2014-11-171-2/+14
| | | | | | | | reduce static table size and number of relocation entries. Indices into the table are stored in each MCRegisterClass instead of a pointer. A new method, getRegClassName, is added to MCRegisterInfo and TargetRegisterInfo to lookup the string in the table. llvm-svn: 222118
* [C++11] Use 'nullptr' in tablegen output files.Craig Topper2014-04-301-5/+5
| | | | llvm-svn: 207611
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-3/+3
| | | | llvm-svn: 205610
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-091-14/+15
| | | | | | class. llvm-svn: 203378
* Fix indentation.Craig Topper2014-02-271-1/+1
| | | | llvm-svn: 202344
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-1/+1
| | | | llvm-svn: 190770
* llvm-tblgen: Stabilize subreg index tables.Benjamin Kramer2013-09-111-2/+2
| | | | | | Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic. llvm-svn: 190514
* Add an OtherPreserved field to the CalleeSaved TableGen class.Jakob Stoklund Olesen2013-08-231-1/+13
| | | | | | | | | | This field specifies registers that are preserved across function calls, but that should not be included in the generates SaveList array. This can be used ot generate regmasks for architectures that save registers through other means, like SPARC's register windows. llvm-svn: 189084
* Using a different loop induction variable than the enclosing scope. No ↵Aaron Ballman2013-07-251-2/+2
| | | | | | functional changes intended. llvm-svn: 187159
* RegPressure: Order the "pressure sets" by number of regunits per set.Andrew Trick2013-07-251-6/+12
| | | | | | This lets heuristics easily pick the most important set to follow. llvm-svn: 187108
* Improve the compression of the tablegen DiffLists by introducing a new sortChad Rosier2013-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 llvm-svn: 185094
* Remove unimplemented definition. Found using [-Wunused-member-function].Jakub Staszak2013-06-061-2/+0
| | | | llvm-svn: 183426
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-2/+2
| | | | | | | This also makes TableGen able to compute sizes/offsets of synthesized indices representing tuples. llvm-svn: 183061
* Add a way to define the bit range covered by a SubRegIndex.Ahmed Bougacha2013-05-311-2/+18
| | | | | | | | | | | | | NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change the instances of SubRegIndex that have a comps template arg to use the ComposedSubRegIndex class instead. In TableGen land, this adds Size and Offset attributes to SubRegIndex, and the ComposedSubRegIndex class, for which the Size and Offset are computed by TableGen. This also adds an accessor in MCRegisterInfo, and Size/Offsets for the X86 and ARM subreg indices. llvm-svn: 183020
* Remove the MCRegAliasIterator tables and compute the aliases dynamically.Chad Rosier2013-05-281-14/+3
| | | | | | | | | | | | | | | | | | | | The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of dynamically computing the aliases is that the iterator does not guarantee that the entries are ordered or that duplicates have been removed. The documentation implies this is a safe assumption and I found no clients that requires these attributes (i.e., strict ordering and uniqueness). My local LNT tester results showed no execution-time failures or significant compile-time regressions (i.e., beyond what I would consider noise) for -O0g, -O2 and -O3 runs on x86_64 and i386 configurations. rdar://12906217 llvm-svn: 182783
* Add TargetRegisterInfo::getCoveringLanes().Jakob Stoklund Olesen2013-05-161-1/+3
| | | | | | | | This lane mask provides information about which register lanes completely cover super-registers. See the block comment before getCoveringLanes(). llvm-svn: 182034
* Use ArrayRef<MVT::SimpleValueType> when possible.Jakob Stoklund Olesen2013-03-171-1/+1
| | | | | | | Not passing vector references around makes it possible to use SmallVector in most places. llvm-svn: 177235
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