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path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-5/+5
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. llvm-svn: 170610
* RegisterPresssureTracker: Track live physical register by unit.Andrew Trick2012-12-051-2/+6
| | | | | | | | This is much simpler to reason about, more efficient, and fixes some corner cases involving implicit super-register defs. Fixed rdar://12797931. llvm-svn: 169425
* RegisterPressure API. Add support for physical register units.Andrew Trick2012-12-051-10/+70
| | | | | | | | | | | | | At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. llvm-svn: 169360
* Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen2012-11-291-7/+7
| | | | | | Use this type for arrays of physical registers. llvm-svn: 168850
* Generate a table-driven version of TRI::composeSubRegIndices().Jakob Stoklund Olesen2012-11-011-26/+102
| | | | | | | | | | Explicitly allow composition of null sub-register indices, and handle that common case in an inlinable stub. Use a compressed table implementation instead of the previous nested switches which generated pretty bad code. llvm-svn: 167190
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-1/+1
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* tblgen: Use semantically correct RTTI functions.Sean Silva2012-10-101-1/+1
| | | | | | Also, some minor cleanup. llvm-svn: 165647
* tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.Sean Silva2012-10-101-2/+2
| | | | | | | | | | Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>. That will happen in a future patch. There are also two dyn_cast_or_null<>'s slipped in instead of dyn_cast<>'s, since they were causing crashes with just dyn_cast<>. llvm-svn: 165646
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-7/+7
| | | | llvm-svn: 163999
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-111-4/+12
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. llvm-svn: 163630
* Clean the sub-reg index composition maps at emission.Jakob Stoklund Olesen2012-09-111-2/+2
| | | | | | | Preserve the Composites map in the CodeGenSubRegIndex class so it can be used to determine which sub-register indices can actually be composed. llvm-svn: 163629
* Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.Jakob Stoklund Olesen2012-09-111-2/+2
| | | | | | | | Apparently, NumSubRegIndices was completely unused before. Adjust it by one to include the null subreg index, just like getNumRegs() includes the null register. llvm-svn: 163628
* Make synthesized sub-register indexes available in the target namespace.Jakob Stoklund Olesen2012-08-151-13/+2
| | | | | | | | | | | TableGen sometimes synthesizes missing sub-register indexes. Emit these indexes as enumerators in the target namespace along with the user-defined ones. Also take this opportunity to stop creating new Record objects for synthetic indexes. llvm-svn: 161964
* Eliminate the large XXXSubRegTable constant arrays.Jakob Stoklund Olesen2012-07-271-53/+31
| | | | | | | | | | | These tables were indexed by [register][subreg index] which made them, very large and sparse. Replace them with lists of sub-register indexes that match the existing lists of sub-registers. MCRI::getSubReg() becomes a very short linear search, like getSubRegIndex() already was. llvm-svn: 160843
* Differentially encode all MC register lists.Jakob Stoklund Olesen2012-07-251-44/+30
| | | | | | | This simplifies MCRegisterInfo and shrinks the target descriptions a bit more. llvm-svn: 160758
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-9/+54
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Didn't mean to export this function.Jakob Stoklund Olesen2012-05-311-0/+1
| | | | llvm-svn: 157756
* Emit register unit root tables.Jakob Stoklund Olesen2012-05-311-0/+17
| | | | | | | | | | Each register unit has one or two root registers. The full set of registers containing a given register unit can be computed as the union of the root registers and their super-registers. Provide an MCRegUnitRootIterator class to enumerate the roots. llvm-svn: 157753
* Print uint16_t numbers without a sign.Jakob Stoklund Olesen2012-05-301-1/+1
| | | | | | It seems I broke C++11. llvm-svn: 157711
* Emit register unit lists for each register.Jakob Stoklund Olesen2012-05-291-3/+75
| | | | | | | | | | | | | | | | Register units are already used internally in TableGen to compute register pressure sets and overlapping registers. This patch makes them available to the code generators. The register unit lists are differentially encoded so they can be reused for many related registers. This keeps the total size of the lists below 200 bytes for most targets. ARM has the largest table at 560 bytes. Add an MCRegUnitIterator for traversing the register unit lists. It provides an abstract interface so the representation can be changed in the future without changing all clients. llvm-svn: 157650
* Compress MCRegisterInfo register name tables.Jakob Stoklund Olesen2012-05-251-3/+16
| | | | | | | Store (debugging) register names as offsets into a string table instead of as char pointers. llvm-svn: 157449
* Use RegUnits to compute overlapping registers.Jakob Stoklund Olesen2012-05-161-3/+2
| | | | | | | | | | | TableGen already computes register units as the basic unit of interference. We can use that to compute the set of overlapping registers. This means that we can easily compute overlap sets for one register at a time. There is no benefit to computing all registers at once. llvm-svn: 156960
* TableGen'erate mapping physical registers to encoding values.Jim Grosbach2012-05-151-4/+26
| | | | | | | | | | | Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. llvm-svn: 156829
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-041-51/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-34/+1
| | | | | | TargetRegisterClass now gives access to the necessary tables. llvm-svn: 156122
* Add TargetRegisterClass::getSuperRegIndices().Jakob Stoklund Olesen2012-05-031-4/+4
| | | | | | | | This is a pointer into one of the tables used by getMatchingSuperRegClass(). It makes it possible to use a shared implementation of that function. llvm-svn: 156121
* Emit SuperRegMasks as part of the existing SubClassMask arrays.Jakob Stoklund Olesen2012-05-031-102/+83
| | | | | | | | | The RC->getSubClassMask() pointer now points to a sequence of register class bit masks. The first bit mask is the normal sub-class mask. The following masks are super-reg class masks used by getMatchingSuperRegClass(). llvm-svn: 156120
* Compress tables for getMatchingSuperRegClass().Jakob Stoklund Olesen2012-05-031-19/+67
| | | | | | | | Many register classes only have a few super-registers, so it is not necessary to keep individual bit masks for all possible sub-register indices. llvm-svn: 156083
* Don't override subreg functions in targets without subregisters.Jakob Stoklund Olesen2012-05-031-42/+39
| | | | | | | | Some targets have no sub-registers at all. Use the TargetRegisterInfo versions of composeSubRegIndices(), getSubClassWithSubReg(), and getMatchingSuperRegClass() for those targets. llvm-svn: 156075
* Remove 'XXXRegisterClass' from tablegen output. Targets should use ↵Craig Topper2012-04-211-3/+0
| | | | | | '&XXXRegClass' instead. llvm-svn: 155270
* TableGen'd RegPressure: Added getPressureSetName.Andrew Trick2012-04-201-1/+13
| | | | llvm-svn: 155234
* tblgen: remove duplicated newlines.Benjamin Kramer2012-04-181-1/+1
| | | | llvm-svn: 155038
* Move a few more warnings to use PrintWarning().Jim Grosbach2012-04-181-2/+4
| | | | llvm-svn: 155027
* Formatting.Jim Grosbach2012-04-181-3/+2
| | | | llvm-svn: 155025
* Tidy up. Add a '.' at the end of the sentence.Jim Grosbach2012-04-181-1/+1
| | | | llvm-svn: 155024
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-111-14/+14
| | | | llvm-svn: 154518
* Tablegen'd regpressure: emit the weighted pressure limit.Andrew Trick2012-04-111-1/+7
| | | | llvm-svn: 154477
* Added register unit sets to the target description.Andrew Trick2012-04-101-0/+76
| | | | | | | | | | This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. llvm-svn: 154374
* Tidy up spacing in some tablegen outputs.Craig Topper2012-04-031-9/+7
| | | | llvm-svn: 153937
* Emit the LLVM<->DWARF register mapping as a sorted table and use binary ↵Benjamin Kramer2012-04-011-43/+143
| | | | | | | | | | | | | | | search to do the lookup. This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated by recent inliner changes but the methods were already enormous with the old inline cost computation. The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table. I didn't implement that optimization yet to avoid potentially changing functionality. There is still some duplication both in tablegen and the generated code that should be cleaned up eventually. llvm-svn: 153837
* Reapply 153764 and 153761 with a fix.Jakob Stoklund Olesen2012-03-301-101/+76
| | | | | | | | | Use an explicit comparator instead of the default. The sets are sorted, but not using the default comparator. Hopefully, this will unbreak the Linux builders. llvm-svn: 153772
* Revert 153764 and 153761. They broke a --enable-optimized --enable-assertionsRafael Espindola2012-03-301-75/+101
| | | | | | --enable-expensive-checks build. llvm-svn: 153771
* Compress SimpleValueType lists by sharing.Jakob Stoklund Olesen2012-03-301-20/+13
| | | | | | Many register classes have the same value types. Share the table space. llvm-svn: 153764
* Compress register lists by sharing suffixes.Jakob Stoklund Olesen2012-03-301-81/+62
| | | | | | | | TableGen emits lists of sub-registers, super-registers, and overlaps. Put them all in a single table and use a SequenceToOffsetTable to share suffixes. llvm-svn: 153761
* Add more constness to CodeGenRegisters.Jakob Stoklund Olesen2012-03-291-2/+2
| | | | llvm-svn: 153667
* Add asserts to ensure that values will fit into the tables.Craig Topper2012-03-061-1/+16
| | | | llvm-svn: 152104
* Shrink and reorder fields in MCRegisterClass to reduce size of static data.Craig Topper2012-03-051-5/+5
| | | | llvm-svn: 152019
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-7/+7
| | | | | | static data size. llvm-svn: 152016
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-2/+2
| | | | llvm-svn: 152001
* Use uint16_t instead of unsigned to store registers in reg classes. Reduces ↵Craig Topper2012-03-041-11/+11
| | | | | | static data size. llvm-svn: 151998
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