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path: root/llvm/utils/TableGen/FastISelEmitter.cpp
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* Implement major new fastisel functionality: the matcher can now handle ↵Chris Lattner2011-04-181-51/+222
| | | | | | | | | | | | | | | | | | | | | | | immediates with value constraints on them (when defined as ImmLeaf's). This is particularly important for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand, which has a value constraint. Before this patch we ended up iseling the examples into such amazing code as: movabsq $7, %rax imulq %rax, %rdi movq %rdi, %rax ret now we produce: imulq $7, %rdi, %rax ret This dramatically shrinks the generated code at -O0 on x86-64. llvm-svn: 129691
* introduce a new OpKind abstraction which wraps up operand flavors in a tidy ↵Chris Lattner2011-04-171-22/+48
| | | | | | | | little wrapper. No functionality change. llvm-svn: 129680
* change OperandsSignature to use SmallVector<char> instead of std::vector<string>Chris Lattner2011-04-171-16/+16
| | | | | | since the strings are always exactly one character, and there are usually only 2-3 operands. llvm-svn: 129678
* remove some debugging code I added.Chris Lattner2011-04-171-5/+0
| | | | llvm-svn: 129668
* 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.llChris Lattner2011-04-171-9/+16
| | | | | | | | | | 2. implement rdar://9289501 - fast isel should fold trivial multiplies to shifts 3. teach tblgen to handle shift immediates that are different sizes than the shifted operands, eliminating some code from the X86 fast isel backend. 4. Have FastISel::SelectBinaryOp use (the poorly named) FastEmit_ri_ function instead of FastEmit_ri to simplify code. llvm-svn: 129666
* Add source Record* reference to PatternToMatch. Allows better diagnostics.Jim Grosbach2010-12-071-7/+3
| | | | llvm-svn: 121196
* Trailing whitespace.Jim Grosbach2010-12-071-29/+29
| | | | llvm-svn: 121167
* Change assert to diagnostic. Message still needs work, but it's better thanJim Grosbach2010-12-071-3/+9
| | | | | | an assert, at least. llvm-svn: 121166
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-2/+2
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* Allow strict subclasses of register classes, this way we can handleEric Christopher2010-08-251-2/+3
| | | | | | | | | | ARM instructions with: foo GPR, rGPR which happens a lot. llvm-svn: 112025
* Fix comment.Eric Christopher2010-08-241-2/+2
| | | | llvm-svn: 111996
* Remove predicate workaround, we're going to require that predicateEric Christopher2010-08-171-9/+0
| | | | | | and optional def operands are handled in the backend support. llvm-svn: 111220
* Filter out patterns that have PredicateOperands.Eric Christopher2010-07-281-0/+12
| | | | llvm-svn: 109572
* 80-col.Eric Christopher2010-07-261-2/+4
| | | | llvm-svn: 109407
* Hack around extracts that aren't easy to process.Eric Christopher2010-07-211-0/+4
| | | | llvm-svn: 109043
* Replace copyRegToReg with COPY in FastISelEmitter.Jakob Stoklund Olesen2010-07-111-13/+9
| | | | llvm-svn: 108071
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-2/+2
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* These changes should have accompanied r107943.Dan Gohman2010-07-091-2/+2
| | | | llvm-svn: 107947
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-2/+2
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-2/+2
| | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. llvm-svn: 107791
* Minor code simplification.Dan Gohman2010-05-271-9/+9
| | | | llvm-svn: 104845
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-241-8/+11
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
* Add initial kill flag support to FastISel.Dan Gohman2010-05-111-5/+5
| | | | llvm-svn: 103529
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* add plumbing for handling multiple result nodes Chris Lattner2010-03-241-1/+3
| | | | | | in some more places. llvm-svn: 99366
* major surgery on tblgen: generalize TreePatternNodeChris Lattner2010-03-191-7/+14
| | | | | | | | | to maintain a list of types (one for each result of the node) instead of a single type. There are liberal hacks added to emulate the old behavior in various situations, but they can start disolving now. llvm-svn: 98999
* look up instructions by record, not by name.Chris Lattner2010-03-191-1/+1
| | | | llvm-svn: 98904
* Completely rewrite tblgen's type inference mechanism,Chris Lattner2010-03-151-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! llvm-svn: 98534
* Don't use the ISD::NodeType enum for SDNode opcodes, as CodeGenDan Gohman2010-01-051-1/+1
| | | | | | | uses several kinds of opcode values which are not declared within that enum. This fixes PR5946. llvm-svn: 92794
* Remove some unused variables and methods warned about byDuncan Sands2009-09-061-1/+0
| | | | | | icc (#177, partial). Patch by Erick Tryzelaar. llvm-svn: 81106
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-16/+16
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-13/+13
| | | | | | own struct type. llvm-svn: 78610
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-10/+9
| | | | | | | | - Sorry, I can't help myself. - No intended functionality change. llvm-svn: 74742
* TableGen for fast isel seems to assume an 'imm'Dale Johannesen2009-05-211-2/+2
| | | | | | | | operand is the last in a pattern. There is no reason this should be true (although apparently it always is right now). llvm-svn: 72232
* Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and ↵Evan Cheng2009-01-221-2/+3
| | | | | | SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. llvm-svn: 62762
* Add support for having multiple predicates on a TreePatternNode.Dan Gohman2008-10-151-2/+2
| | | | | | | | This will allow predicates to be composed, which will allow the predicate definitions to become less redundant, and eventually will allow DAGISelEmitter.cpp to emit less redundant code. llvm-svn: 57562
* Move the primary fast-isel top-level comments to FastISel.cpp, whereDan Gohman2008-09-301-24/+6
| | | | | | they'll be a little more visible. Also, update and reword them a bit. llvm-svn: 56877
* Correctly handle physical register inputs. They are not explicit input ↵Evan Cheng2008-09-081-9/+30
| | | | | | operands in the resulting machine instrs. llvm-svn: 55893
* Fix indentation of generated code.Evan Cheng2008-09-071-1/+1
| | | | llvm-svn: 55876
* Ignore multi-instruction patterns. e.g.Evan Cheng2008-09-071-0/+14
| | | | | | | def : Pat<(i8 (trunc GR32:$src)), (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))> llvm-svn: 55875
* Let tblgen only generate fastisel routines, not the class definition. This ↵Evan Cheng2008-09-031-106/+5
| | | | | | makes it easier for targets to define its own fastisel class. llvm-svn: 55679
* Add initial support for fast isel of instructions that have inputs pinned to ↵Owen Anderson2008-08-291-19/+107
| | | | | | physical registers. llvm-svn: 55545
* Add a target callback for FastISel.Dan Gohman2008-08-281-0/+8
| | | | llvm-svn: 55512
* Add support for fast-isel of opcodes that require use of extract_subreg. ↵Owen Anderson2008-08-281-21/+43
| | | | | | Because of how extract_subreg is treated, it requires special case handling. llvm-svn: 55480
* Update a comment to reflect recent changes.Dan Gohman2008-08-271-1/+1
| | | | llvm-svn: 55418
* Basic FastISel support for floating-point constants.Dan Gohman2008-08-271-0/+13
| | | | llvm-svn: 55401
* Refactor a bunch of FastISelEmitter code into a helper class, andDan Gohman2008-08-261-27/+63
| | | | | | | put each major step in a separate function. This makes the high level sequence of events easier to follow. llvm-svn: 55385
* We need to check that the return type is correct, even in cases where we don'tOwen Anderson2008-08-261-0/+3
| | | | | | have a return type that differs from the operand types. llvm-svn: 55376
* Throw the switch to allow FastISel to emit instructions whose return types ↵Owen Anderson2008-08-261-9/+16
| | | | | | different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes. llvm-svn: 55349
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