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author | Chris Lattner <sabre@nondot.org> | 2010-03-15 06:00:16 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-03-15 06:00:16 +0000 |
commit | cabe037b2d98d4d9796828b0e31f531affe1e54f (patch) | |
tree | 86776802d024ebe17462e223115a8367c0b72cbf /llvm/utils/TableGen/FastISelEmitter.cpp | |
parent | 227aa3595b50be335a03876a6f93696134e49395 (diff) | |
download | bcm5719-llvm-cabe037b2d98d4d9796828b0e31f531affe1e54f.tar.gz bcm5719-llvm-cabe037b2d98d4d9796828b0e31f531affe1e54f.zip |
Completely rewrite tblgen's type inference mechanism,
changing the primary datastructure from being a
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!
This changes more things than I remember, but one major
innovation here is that it enforces that named input
values agree in type with their output values.
This also eliminates code that transparently assumes (in
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.
This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.
With all the recent target changes, this causes no
functionality change!
llvm-svn: 98534
Diffstat (limited to 'llvm/utils/TableGen/FastISelEmitter.cpp')
-rw-r--r-- | llvm/utils/TableGen/FastISelEmitter.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp index f589bcc9e45..b94ded64526 100644 --- a/llvm/utils/TableGen/FastISelEmitter.cpp +++ b/llvm/utils/TableGen/FastISelEmitter.cpp @@ -73,10 +73,9 @@ struct OperandsSignature { if (!Op->getPredicateFns().empty()) return false; // For now, filter out any operand with multiple values. - if (Op->getExtTypes().size() != 1) - return false; + assert(Op->hasTypeSet() && "Type infererence not done?"); // For now, all the operands must have the same type. - if (Op->getTypeNum(0) != VT) + if (Op->getType() != VT) return false; if (!Op->isLeaf()) { if (Op->getOperator()->getName() == "imm") { @@ -296,10 +295,10 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { Record *InstPatOp = InstPatNode->getOperator(); std::string OpcodeName = getOpcodeName(InstPatOp, CGP); - MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0); + MVT::SimpleValueType RetVT = InstPatNode->getType(); MVT::SimpleValueType VT = RetVT; if (InstPatNode->getNumChildren()) - VT = InstPatNode->getChild(0)->getTypeNum(0); + VT = InstPatNode->getChild(0)->getType(); // For now, filter out instructions which just set a register to // an Operand or an immediate, like MOV32ri. |