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* [TableGen] Correct comments for end of namespace. NFCBjorn Pettersson2019-08-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: Update end-of-namespace comments generated by tablegen emitters to fulfill the rules setup by clang-tidy's llvm-namespace-comment checker. Fixed a few end-of-namespace comments in the tablegen source code as well. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: craig.topper, stoklund, dschuff, sbc100, jgravelle-google, aheejin, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66396 llvm-svn: 369865
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [WebAssembly] Initial Disassembler.Sam Clegg2018-05-101-0/+9
| | | | | | | | | | | | | | | | | | | | | This implements a new table-gen emitter to create tables for a wasm disassembler, and a dissassembler to use them. Comes with 2 tests, that tests a few instructions manually. Is also able to disassemble large .wasm files with objdump reasonably. Not working so well, to be addressed in followups: - objdump appears to be passing an incorrect starting point. - since the disassembler works an instruction at a time, and it is disassembling stack instruction, it has no idea of pseudo register assignments. These registers are required for the instruction printing code that follows. For now, all such registers appear in the output as $0. Patch by Wouter van Oortmerssen Differential Revision: https://reviews.llvm.org/D45848 llvm-svn: 332052
* Fix layering by moving X86DisassemblerDecoderCommon to SupportDavid Blaikie2018-03-231-2/+2
| | | | | | | | | This is used from llvm tblgen and the X86Disassembler - the only common library (apart from TableGen, which probably doesn't make sense to have as a dependency from a release tool (rather than a use-while-building-llvm tool) of LLVM) llvm-svn: 328393
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+1
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer2016-06-081-6/+5
| | | | | | | Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
* [TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead ↵Craig Topper2016-02-011-1/+1
| | | | | | of accidentally copying to a vector. llvm-svn: 259336
* [TableGen] Improve decoding options for non-orthogonal instructionsPetr Pavlu2015-07-151-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When FixedLenDecoder matches an input bitpattern of form [01]+ with an instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are mixed/variable bits) it passes the input bitpattern to a specific instruction decoder method which then makes a final decision whether the bitpattern is a valid instruction or not. This means the decoder must handle all possible values of the variable bits which sometimes leads to opcode rewrites in the decoder method when the instructions are not fully orthogonal. The patch provides a way for the decoder method to say that when it returns Fail it does not necessarily mean the bitpattern is invalid, but rather that the bitpattern is definitely not an instruction that is recognized by the decoder method. The decoder can then try to match the input bitpattern with other possible instruction bitpatterns. For example, this allows to solve a situation on AArch64 where the `MSR (immediate)` instruction has form: 1101 0101 0000 0??? 0100 ???? ???1 1111 but not all values of the ? bits are allowed. The rejected values should be handled by the `extended MSR (register)` instruction: 1101 0101 000? ???? ???? ???? ???? ???? The decoder will first try to decode an input bitpattern that matches both bitpatterns as `MSR (immediate)` but currently this puts the decoder method of `MSR (immediate)` into a situation when it must be able to decode all possible values of the ? bits, i.e. it would need to rewrite the instruction to `MSR (register)` when it is not `MSR (immediate)`. The patch allows to specify that the decoder method cannot determine if the instruction is valid for all variable values. The decoder method can simply return Fail when it knows it is definitely not `MSR (immediate)`. The decoder will then backtrack the decoding and find that it can match the input bitpattern with the more generic `MSR (register)` bitpattern too. Differential Revision: http://reviews.llvm.org/D7174 llvm-svn: 242274
* AArch64/ARM64: implement diagnosis of unpredictable loads & storesTim Northover2014-05-061-4/+7
| | | | llvm-svn: 208091
* Don't use PrintFatalError(which calls exit) for 'Primary decode conflict'. ↵Craig Topper2014-01-051-3/+4
| | | | | | Just skip emitting the table. This way the main function will delete the output file instead of it remaining empty and confusing dependency checks if build is invoked a second time. llvm-svn: 198529
* Add AArch64 as an experimental target.Tim Northover2013-01-311-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
* Remove exception handling usage from tblgen.Joerg Sonnenberger2012-10-251-4/+2
| | | | | | | | | | | Most places can use PrintFatalError as the unwinding mechanism was not used for anything other than printing the error. The single exception was CodeGenDAGPatterns.cpp, where intermediate errors during type resolution were ignored to simplify incremental platform development. This use is replaced by an error flag in TreePattern and bailout earlier in various places if it is set. llvm-svn: 166712
* Write llvm-tblgen backends as functions instead of sub-classes.Jakob Stoklund Olesen2012-06-111-21/+26
| | | | | | | | | The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
* Remove the old-style ARM disassembler, which is no longer used.Owen Anderson2011-11-091-1/+0
| | | | llvm-svn: 144243
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-2/+2
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-071-2/+3
| | | | | | predicate checking to the Disassembler. llvm-svn: 139250
* Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy2011-09-011-3/+3
| | | | llvm-svn: 138948
* Allow the MCDisassembler to return a "soft fail" status code, indicating an ↵Owen Anderson2011-08-171-0/+10
| | | | | | | | instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. Patch by James Molloy. llvm-svn: 137830
* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-7/+0
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Consolidate some TableGen diagnostic helper functions.Jim Grosbach2011-06-211-0/+1
| | | | | | | TableGen had diagnostic printers sprinkled about in a few places. Pull them together into a single location in Error.cpp. llvm-svn: 133568
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-6/+6
| | | | llvm-svn: 128826
* Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson2011-02-181-2/+3
| | | | | | | | | | | | | fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. llvm-svn: 125966
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-1/+1
| | | | llvm-svn: 121659
* Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen2010-04-021-0/+8
| | | | | | | | | | backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-2/+2
| | | | | | | to a vector that CGT stores instead of synthesizing it on every call. llvm-svn: 98910
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-0/+8
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-0/+99
| | | | | | | | | | | | | | | | | | | | incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. llvm-svn: 91749
* Sketch TableGen disassembler emitter, based on patch by Sean Callanan.Daniel Dunbar2009-11-251-0/+30
llvm-svn: 89833
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