| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) s... | Johnny Chen | 2011-04-22 | 1 | -0/+5 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -2/+2 |
| * | Thumb disassembler was erroneously rejecting "blx sp" instruction. | Johnny Chen | 2011-04-11 | 1 | -0/+4 |
| * | delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ins... | Johnny Chen | 2011-03-25 | 1 | -0/+5 |
| * | The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ... | Johnny Chen | 2011-03-24 | 1 | -2/+2 |
| * | The ARM disassembler was confused with the 16-bit tSTMIA instruction. | Johnny Chen | 2011-03-24 | 1 | -0/+5 |
| * | ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder wa... | Johnny Chen | 2011-03-24 | 1 | -0/+4 |
| * | Remove no-longer-correct special case for disasm of ARM BL instructions. | Jim Grosbach | 2011-03-12 | 1 | -5/+0 |
| * | Pseudo-ize the ARM 'B' instruction. | Jim Grosbach | 2011-03-11 | 1 | -3/+0 |
| * | Remove dead code. These ARM instruction definitions no longer exist. | Jim Grosbach | 2011-03-11 | 1 | -8/+0 |
| * | Remove dead code. These ARM instruction definitions no longer exist. | Jim Grosbach | 2011-03-11 | 1 | -9/+0 |
| * | Pseudo-ize VMOVDcc and VMOVScc. | Jim Grosbach | 2011-03-11 | 1 | -3/+2 |
| * | Remove dead code. These ARM instruction definitions don't exist. | Jim Grosbach | 2011-03-11 | 1 | -14/+0 |
| * | ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same | Jim Grosbach | 2011-03-11 | 1 | -6/+0 |
| * | Remove dead code. These ARM instruction definitions don't exist. | Jim Grosbach | 2011-03-11 | 1 | -10/+0 |
| * | ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q | Jim Grosbach | 2011-03-11 | 1 | -4/+1 |
| * | ARM VREV64df and VREV64qf can just be patterns. The instruction is the same | Jim Grosbach | 2011-03-11 | 1 | -7/+0 |
| * | Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. | Jim Grosbach | 2011-03-11 | 1 | -6/+6 |
| * | Properly pseudo-ize MOVCCr and MOVCCs. | Jim Grosbach | 2011-03-10 | 1 | -4/+3 |
| * | Memory barrier instructions don't need special handling in tblgen anymore. | Jim Grosbach | 2011-03-10 | 1 | -3/+1 |
| * | TableGen should not ignore BX instructions for the ARM disassembler. pr9368. | Bob Wilson | 2011-03-03 | 1 | -1/+1 |
| * | pr9367: Add missing predicated BLX instructions. | Bob Wilson | 2011-03-03 | 1 | -1/+1 |
| * | Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for fi... | Owen Anderson | 2011-02-18 | 1 | -96/+101 |
| * | Add support for parsing and encoding ARM's official syntax for the BFI instru... | Bruno Cardoso Lopes | 2011-01-18 | 1 | -0/+4 |
| * | Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 | Jim Grosbach | 2010-12-14 | 1 | -8/+3 |
| * | Remove the rest of the *_sfp Neon instruction patterns. | Bob Wilson | 2010-12-13 | 1 | -5/+0 |
| * | Merge DEBUG statements. | Bill Wendling | 2010-12-13 | 1 | -8/+8 |
| * | eliminate the Records global variable, patch by Garrison Venn! | Chris Lattner | 2010-12-13 | 1 | -3/+3 |
| * | Remove reference to the CMPz instruction patterns for ARM. | Jim Grosbach | 2010-12-07 | 1 | -8/+1 |
| * | I did it wrong. Don't disregard these encodings here. | Bill Wendling | 2010-12-03 | 1 | -7/+0 |
| * | Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr | Bill Wendling | 2010-12-03 | 1 | -0/+7 |
| * | The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e., | Jim Grosbach | 2010-11-30 | 1 | -5/+0 |
| * | Tidy up. | Jim Grosbach | 2010-11-30 | 1 | -2/+3 |
| * | Delete a few no longer needed references to pseudos. | Jim Grosbach | 2010-11-30 | 1 | -4/+0 |
| * | Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw | Jim Grosbach | 2010-11-29 | 1 | -6/+1 |
| * | Rename t2 TBB and TBH instructions to reference that they encode the jump table | Jim Grosbach | 2010-11-29 | 1 | -1/+1 |
| * | Merge System into Support. | Michael J. Spencer | 2010-11-29 | 1 | -1/+1 |
| * | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 | 1 | -5/+5 |
| * | factor the operand list (and related fields/operations) out of | Chris Lattner | 2010-11-01 | 1 | -2/+2 |
| * | A few 80 column cleanups | Jim Grosbach | 2010-10-08 | 1 | -1/+1 |
| * | Move checking for t2MOVCCi16 to the right place. | Jim Grosbach | 2010-10-07 | 1 | -6/+7 |
| * | Fix typo in comment. | Nick Lewycky | 2010-10-07 | 1 | -1/+1 |
| * | Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. | Jim Grosbach | 2010-10-07 | 1 | -5/+5 |
| * | Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. | Jim Grosbach | 2010-10-07 | 1 | -7/+7 |
| * | Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling. | Jim Grosbach | 2010-10-06 | 1 | -6/+5 |
| * | Fix a comment typo. | Bob Wilson | 2010-08-27 | 1 | -1/+1 |
| * | Add a separate ARM instruction format for Saturate instructions. | Bob Wilson | 2010-08-11 | 1 | -30/+29 |
| * | Changes to ARM tail calls, mostly cosmetic. | Dale Johannesen | 2010-07-08 | 1 | -2/+2 |
| * | An attempt to fix the problem Anton reported with | Dale Johannesen | 2010-06-18 | 1 | -0/+1 |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 | 1 | -1/+2 |
