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path: root/llvm/utils/TableGen/ARMDecoderEmitter.cpp
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* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+5
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-2/+2
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+4
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-251-0/+5
| | | | | | instructions, and add a test case for that. llvm-svn: 128249
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-241-2/+2
| | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. llvm-svn: 128247
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+5
| | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. llvm-svn: 128246
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+4
| | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. llvm-svn: 128234
* Remove no-longer-correct special case for disasm of ARM BL instructions.Jim Grosbach2011-03-121-5/+0
| | | | llvm-svn: 127517
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-111-3/+0
| | | | llvm-svn: 127510
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-8/+0
| | | | llvm-svn: 127509
* Remove dead code. These ARM instruction definitions no longer exist.Jim Grosbach2011-03-111-9/+0
| | | | llvm-svn: 127508
* Pseudo-ize VMOVDcc and VMOVScc.Jim Grosbach2011-03-111-3/+2
| | | | llvm-svn: 127506
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-14/+0
| | | | llvm-svn: 127491
* ARM VDUPfd and VDUPfq can just be patterns. The instruction is the sameJim Grosbach2011-03-111-6/+0
| | | | | | as for VDUP32d and VDUP32q, respectively. llvm-svn: 127489
* Remove dead code. These ARM instruction definitions don't exist.Jim Grosbach2011-03-111-10/+0
| | | | llvm-svn: 127488
* ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32qJim Grosbach2011-03-111-4/+1
| | | | | | and VDUPLN32d, respectively. llvm-svn: 127486
* ARM VREV64df and VREV64qf can just be patterns. The instruction is the sameJim Grosbach2011-03-111-7/+0
| | | | | | as for VREV64d32 and VREV64q32, respectively. llvm-svn: 127485
* Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos.Jim Grosbach2011-03-111-6/+6
| | | | llvm-svn: 127445
* Properly pseudo-ize MOVCCr and MOVCCs.Jim Grosbach2011-03-101-4/+3
| | | | llvm-svn: 127434
* Memory barrier instructions don't need special handling in tblgen anymore.Jim Grosbach2011-03-101-3/+1
| | | | llvm-svn: 127419
* TableGen should not ignore BX instructions for the ARM disassembler. pr9368.Bob Wilson2011-03-031-1/+1
| | | | llvm-svn: 126931
* pr9367: Add missing predicated BLX instructions.Bob Wilson2011-03-031-1/+1
| | | | | | Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. llvm-svn: 126915
* Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson2011-02-181-96/+101
| | | | | | | | | | | | | fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. llvm-svn: 125966
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+4
| | | | | | instruction llvm-svn: 123770
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-8/+3
| | | | llvm-svn: 121798
* Remove the rest of the *_sfp Neon instruction patterns.Bob Wilson2010-12-131-5/+0
| | | | | | | | | | | | | Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions. This change made a big difference in the code generated for the CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing a fine job, but some instructions that were previously moved outside the loop are not moved now. It's using fewer VFP registers now, which is generally a good thing, so I think the estimates for register pressure changed and that affected the LICM behavior. Since that isn't obviously wrong, I've just changed the test file. This completes the work for Radar 8711675. llvm-svn: 121730
* Merge DEBUG statements.Bill Wendling2010-12-131-8/+8
| | | | llvm-svn: 121660
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-3/+3
| | | | llvm-svn: 121659
* Remove reference to the CMPz instruction patterns for ARM.Jim Grosbach2010-12-071-8/+1
| | | | llvm-svn: 121180
* I did it wrong. Don't disregard these encodings here.Bill Wendling2010-12-031-7/+0
| | | | llvm-svn: 120786
* Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gprBill Wendling2010-12-031-0/+7
| | | | | | instructions. They are handled as special moves, but encoded as a normal move. llvm-svn: 120779
* The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,Jim Grosbach2010-11-301-5/+0
| | | | | | | no extra encoding information), so we no longer need to special case them here. llvm-svn: 120444
* Tidy up.Jim Grosbach2010-11-301-2/+3
| | | | llvm-svn: 120443
* Delete a few no longer needed references to pseudos.Jim Grosbach2010-11-301-4/+0
| | | | llvm-svn: 120441
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-291-6/+1
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* Merge System into Support.Michael J. Spencer2010-11-291-1/+1
| | | | llvm-svn: 120298
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-5/+5
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-2/+2
| | | | | | CodeGenInstruction into its own helper class. No functionality change. llvm-svn: 117893
* A few 80 column cleanupsJim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116069
* Move checking for t2MOVCCi16 to the right place.Jim Grosbach2010-10-071-6/+7
| | | | llvm-svn: 115994
* Fix typo in comment.Nick Lewycky2010-10-071-1/+1
| | | | llvm-svn: 115986
* Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.Jim Grosbach2010-10-071-5/+5
| | | | llvm-svn: 115890
* Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach2010-10-071-7/+7
| | | | llvm-svn: 115884
* Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.Jim Grosbach2010-10-061-6/+5
| | | | llvm-svn: 115841
* Fix a comment typo.Bob Wilson2010-08-271-1/+1
| | | | llvm-svn: 112302
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-30/+29
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-081-2/+2
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* An attempt to fix the problem Anton reported withDale Johannesen2010-06-181-0/+1
| | | | | | | ARM tail calls. Don't know if it works, but it doesn't break Darwin. llvm-svn: 106309
* Next round of tail call changes. Register used in a tailDale Johannesen2010-06-151-1/+2
| | | | | | | | call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. llvm-svn: 106053
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