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* move testcase into appropriate X86 subdirectory.Adrian Prantl2013-03-291-3/+4
| | | | llvm-svn: 178364
* Implement FRINT lowering on PPC using frinHal Finkel2013-03-291-0/+37
| | | | | | | | | | | | | | Like nearbyint, rint can be implemented on PPC using the frin instruction. The complication comes from the fact that rint needs to set the FE_INEXACT flag when the result does not equal the input value (and frin does not do that). As a result, we use a custom inserter which, after the rounding, compares the rounded value with the original, and if they differ, explicitly sets the XX bit in the FPSCR register (which corresponds to FE_INEXACT). Once LLVM has better modeling of the floating-point environment we should be able to (often) eliminate this extra complexity. llvm-svn: 178362
* Split the llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m testcase ↵Adrian Prantl2013-03-291-0/+371
| | | | | | | | into a CFE and LLVM part. rdar://problem/12767564 llvm-svn: 178353
* Remove the old CodePlacementOpt pass.Benjamin Kramer2013-03-295-7/+7
| | | | | | It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1. llvm-svn: 178349
* Add PPC FP rounding instructions fri[mnpz]Hal Finkel2013-03-292-18/+126
| | | | | | | | | These instructions are available on the P5x (and later) and on the A2. They implement the standard floating-point rounding operations (floor, trunc, etc.). One caveat: frin (round to nearest) does not implement "ties to even", and so is only enabled in fast-math mode. llvm-svn: 178337
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-281-0/+2
| | | | | | | | | Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-283-1/+146
| | | | llvm-svn: 178314
* Enhance boolean simplification to handle 16-/64-bit RDRANDMichael Liao2013-03-281-2/+34
| | | | | | | | | - RDRAND always clears the destination value when a random value is not available (i.e. CF == 0). This value is truncated or zero-extended as the false boolean value to be returned. Boolean simplification needs to skip this 'zext' or 'trunc' node. llvm-svn: 178312
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-281-1/+15
| | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic llvm-svn: 178304
* Make Win32 put the SRet address into EAX, fixes PR15556Timur Iskhodzhanov2013-03-281-11/+67
| | | | llvm-svn: 178291
* Specify CPUs on the PPC bswap-load-store testHal Finkel2013-03-281-2/+2
| | | | | | Otherwise, the CHECK-NOT's might trigger depending on the host's CPU. llvm-svn: 178287
* Only enable 64-bit bswap DAG combines for PPC64Hal Finkel2013-03-281-0/+1
| | | | | | | | Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were added for bswap with load/store. This is because these combines are really only valid in 64-bit mode, regardless of the CPU (and this was not being checked). llvm-svn: 178286
* Non optimizable objc_retainBlock calls are not forwarding.Michael Gottesman2013-03-281-2/+2
| | | | | | | | | | | | Since we handle optimizable objc_retainBlocks through strength reduction in OptimizableIndividualCalls, we know that all code after that point will only see non-optimizable objc_retainBlock calls. IsForwarding is only called by functions after that point, so it is ok to just classify objc_retainBlock as non-forwarding. <rdar://problem/13249661>. llvm-svn: 178285
* [ObjCARC] Strength reduce objc_retainBlock -> objc_retain if the ↵Michael Gottesman2013-03-282-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | objc_retainBlock is optimizable. If an objc_retainBlock has the copy_on_escape metadata attached to it AND if the block pointer argument only escapes down the stack, we are allowed to strength reduce the objc_retainBlock to to an objc_retain and thus optimize it. Current there is logic in the ARC data flow analysis to handle this case which is complicated and involved making distinctions in between objc_retainBlock and objc_retain in certain places and considering them the same in others. This patch simplifies said code by: 1. Performing the strength reduction in the initial ARC peephole analysis (ObjCARCOpts::OptimizeIndividualCalls). 2. Changes the ARC dataflow analysis (which runs after the peephole analysis) to consider all objc_retainBlock calls to not be optimizable (since if the call was optimizable, we would have strength reduced it already). This patch leaves in the infrastructure in the ARC dataflow analysis to handle this case, which due to 2 will just be dead code. I am doing this on purpose to separate the removal of the old code from the testing of the new code. <rdar://problem/13249661>. llvm-svn: 178284
* Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.Jyotsna Verma2013-03-281-1/+0
| | | | llvm-svn: 178279
* Remove -O3.Akira Hatanaka2013-03-281-3/+3
| | | | llvm-svn: 178278
* Add the PPC64 ldbrx/stdbrx instructionsHal Finkel2013-03-281-0/+30
| | | | | | | | These are 64-bit load/store with byte-swap, and available on the P7 and the A2. Like the similar instructions for 16- and 32-bit words, these are matched in the target DAG-combine phase against load/store-bswap pairs. llvm-svn: 178276
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-0/+3
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Move test since it depends on the X86 backend.Rafael Espindola2013-03-281-0/+0
| | | | llvm-svn: 178249
* Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma2013-03-281-0/+33
| | | | | | Remove noV4T gp-relative instructions. llvm-svn: 178246
* AArch64: implement GICv3 system registersTim Northover2013-03-283-0/+506
| | | | llvm-svn: 178236
* Add the PPC64 popcntd instructionHal Finkel2013-03-281-0/+41
| | | | | | | PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and tell TTI about it so that popcount-loop recognition will know about it. llvm-svn: 178233
* [tsan] make sure memset/memcpy/memmove are not inlined in tsan modeKostya Serebryany2013-03-281-0/+33
| | | | llvm-svn: 178230
* Revert "Updated ELF relocation test for .eh_frame section"Michael Gottesman2013-03-281-26/+4
| | | | | | | | This reverts commit c8d65364223a04b179958a50a4bf0f89b21dd7d2. This broke a bunch of the buildbots. llvm-svn: 178222
* Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructionsHal Finkel2013-03-282-4/+412
| | | | | | | | There were a few places where kill flags were not being set correctly, and where 32-bit instruction variants were being used with 64-bit registers. After r178180, this code was being triggered causing llc to assert. llvm-svn: 178220
* Revert "Adding DIImportedModules to DIScopes."David Blaikie2013-03-2895-1240/+1240
| | | | | | | | | This reverts commit 342d92c7a0adeabc9ab00f3f0d88d739fe7da4c7. Turns out we're going with a different schema design to represent DW_TAG_imported_modules so we won't need this extra field. llvm-svn: 178215
* Check if Type is a vector before calling function Type::getVectorNumElements.Akira Hatanaka2013-03-281-0/+15
| | | | llvm-svn: 178208
* This patch follows is a follow up to r178171, which uses the register Preston Gurd2013-03-274-5/+422
| | | | | | | | | | | | | | form of call in preference to memory indirect on Atom. In this case, the patch applies the optimization to the code for reloading spilled registers. The patch also includes changes to sibcall.ll and movgs.ll, which were failing on the Atom buildbot after the first patch was applied. This patch by Sriram Murali. llvm-svn: 178193
* Updated ELF relocation test for .eh_frame sectionJack Carter2013-03-271-4/+26
| | | | | | | | Made sure we were looking a correct section Added Mips32/64 as an extra check Updated llvm-objdump to generate symbolic info for Mips relocations llvm-svn: 178190
* [ms-inline asm] Add support of imm displacement before bracketed memoryChad Rosier2013-03-271-0/+20
| | | | | | | | | | | | | | expression. Specifically, this syntax: ImmDisp [ BaseReg + Scale*IndexReg + Disp ] We don't currently support: ImmDisp [ Symbol ] rdar://13518671 llvm-svn: 178186
* test file name change to correct typoJack Carter2013-03-271-0/+0
| | | | llvm-svn: 178174
* For the current Atom processor, the fastest way to handle a callPreston Gurd2013-03-271-0/+45
| | | | | | | | | | | | | indirect through a memory address is to load the memory address into a register and then call indirect through the register. This patch implements this improvement by modifying SelectionDAG to force a function address which is a memory reference to be loaded into a virtual register. Patch by Sriram Murali. llvm-svn: 178171
* R600/SI: add SETO/SETUO patternsChristian Konig2013-03-272-0/+26
| | | | | | | | 6 more piglit tests. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178145
* Print PPC ZERO as 0 (not r0) even on DarwinHal Finkel2013-03-271-3/+3
| | | | | | | It seems that the Darwin PPC assembler requires r0 to be written as 0 when it means 0 (at least in lwarx/stwcx.). Fixes PR15605. llvm-svn: 178142
* Disable ASan/MSan symbolization of reports in tests.Evgeniy Stepanov2013-03-272-11/+0
| | | | | | It was using an instrumented symbolizer binary, which is a potential fork bomb. llvm-svn: 178139
* Enabling the generation of dependency breakers for partial updates on ↵Silviu Baranga2013-03-272-2/+41
| | | | | | Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32. llvm-svn: 178134
* R600/SI: add cummuting of rev instructionsChristian Konig2013-03-273-3/+3
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178127
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-271-0/+16
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178126
* R600/SI: add srl/sha patterns for SIChristian Konig2013-03-272-0/+28
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178125
* Allocate r0 on PPCHal Finkel2013-03-271-0/+18
| | | | | | | The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. llvm-svn: 178123
* Remove the link register from the GPR classes on PowerPC.Bill Schmidt2013-03-277-15/+15
| | | | | | | | | | | | | | | Some implementation detail in the forgotten past required the link register to be placed in the GPRC and G8RC register classes. This is just wrong on the face of it, and causes several extra intersection register classes to be generated. I found this was having evil effects on instruction scheduling, by causing the wrong register class to be consulted for register pressure decisions. No code generation changes are expected, other than some minor changes in instruction order. Seven tests in the test bucket required minor tweaks to adjust to the new normal. llvm-svn: 178114
* Added back in the test for arc-annotations.Michael Gottesman2013-03-271-0/+307
| | | | | | | | | The test was removed since I had not turned off the test during release builds. This fails since ARC annotations support is conditionally compiled out during release builds. I added the proper requires header to assuage this issue. llvm-svn: 178101
* Adding DIImportedModules to DIScopes.David Blaikie2013-03-2795-1240/+1240
| | | | | | | | | | | | This is just the basic groundwork for supporting DW_TAG_imported_module but I wanted to commit this before pushing support further into Clang or LLVM so that this rather churny change is isolated from the rest of the work. The major churn here is obviously adding another field (within the common DIScope prefix) to all DIScopes (files, classes, namespaces, lexical scopes, etc). This should be the last big churny change needed for DW_TAG_imported_module/using directive support/PR14606. llvm-svn: 178099
* Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel2013-03-272-5/+10
| | | | | | | | | | | | | As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've added some asserts to make sure that we're not). As it turns out, we're not currently handling the Darwin case correctly (I've added a FIXME in the test case). I've tried adding various implied register definitions/uses to force the spill without success, so I'll need to address this later. llvm-svn: 178096
* Add XTEST codegen supportMichael Liao2013-03-261-0/+11
| | | | llvm-svn: 178083
* Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen2013-03-262-3/+3
| | | | | | | | | | | | All Intel CPUs since Yonah look a lot alike, at least at the granularity of the scheduling models. We can add more accurate models for processors that aren't Sandy Bridge if required. Haswell will probably need its own. The Atom processor and anything based on NetBurst is completely different. So are the non-Intel chips. llvm-svn: 178080
* Use multiple virtual registers in PPC CR spillingHal Finkel2013-03-261-17/+23
| | | | | | | | | | | | Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. llvm-svn: 178060
* Update PEI's virtual-register-based scavenging to support multiple ↵Hal Finkel2013-03-261-3/+3
| | | | | | | | | | | | | | | | | | | simultaneous mappings The previous algorithm could not deal properly with scavenging multiple virtual registers because it kept only one live virtual -> physical mapping (and iterated through operands in order). Now we don't maintain a current mapping, but rather use replaceRegWith to completely remove the virtual register as soon as the mapping is established. In order to allow the register scavenger to return a physical register killed by an instruction for definition by that same instruction, we now call RS->forward(I) prior to eliminating virtual registers defined in I. This requires a minor update to forward to ignore virtual registers. These new features will be tested in forthcoming commits. llvm-svn: 178058
* Fix PRFCHW test on non-x86 buildsMichael Liao2013-03-261-1/+1
| | | | | | | - 'prefetch' intrinsics are only lowered when SSE is available. On non-X86 builds, 'generic' CPU is used and stops lowering any prefetch intrinsics. llvm-svn: 178046
* Add PREFETCHW codegen supportMichael Liao2013-03-261-0/+3
| | | | | | - Add 'PRFCHW' feature defined in AVX2 ISA extension llvm-svn: 178040
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