diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-28 19:25:55 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-28 19:25:55 +0000 |
| commit | 31d2956510b8484373fe244547b4f811430a28ff (patch) | |
| tree | 8bdb71b918d6c0746149c1e7a9158abd3a15243b /llvm/test | |
| parent | 772cf466dab6beadf3cab40722cf6cf10342f808 (diff) | |
| download | bcm5719-llvm-31d2956510b8484373fe244547b4f811430a28ff.tar.gz bcm5719-llvm-31d2956510b8484373fe244547b4f811430a28ff.zip | |
Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.
llvm-svn: 178276
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/bswap-load-store.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll index 4f6bfc72991..2aae4150efb 100644 --- a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll +++ b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32 ; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7 define void @STWBRX(i32 %i, i8* %ptr, i32 %off) { @@ -34,18 +35,47 @@ define i16 @LHBRX(i8* %ptr, i32 %off) { ret i16 %tmp6 } +define void @STDBRX(i64 %i, i8* %ptr, i64 %off) { + %tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1] + %tmp1.upgrd.1 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1] + %tmp13 = tail call i64 @llvm.bswap.i64( i64 %i ) ; <i64> [#uses=1] + store i64 %tmp13, i64* %tmp1.upgrd.1 + ret void +} + +define i64 @LDBRX(i8* %ptr, i64 %off) { + %tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1] + %tmp1.upgrd.2 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1] + %tmp = load i64* %tmp1.upgrd.2 ; <i64> [#uses=1] + %tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp ) ; <i64> [#uses=1] + ret i64 %tmp14 +} + declare i32 @llvm.bswap.i32(i32) declare i16 @llvm.bswap.i16(i16) +declare i64 @llvm.bswap.i64(i64) + ; X32: stwbrx ; X32: lwbrx ; X32: sthbrx ; X32: lhbrx +; X32-NOT: ldbrx +; X32-NOT: stdbrx ; X64: stwbrx ; X64: lwbrx ; X64: sthbrx ; X64: lhbrx +; X64-NOT: ldbrx +; X64-NOT: stdbrx + +; PWR7: stwbrx +; PWR7: lwbrx +; PWR7: sthbrx +; PWR7: lhbrx +; PWR7: stdbrx +; PWR7: ldbrx |
