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* [mips][microMIPS] Implement ADDIUSP instructionZoran Jovanovic2014-10-102-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D5084 llvm-svn: 219500
* [mips][microMIPS] Implement JR16 instructionZoran Jovanovic2014-10-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5062 llvm-svn: 219498
* [mips][microMIPS] Implement ADDIUS5 instructionZoran Jovanovic2014-10-102-0/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D5049 llvm-svn: 219495
* ps][microMIPS] Implement JRC instructionZoran Jovanovic2014-10-101-2/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5045 llvm-svn: 219494
* [mips][microMIPS] Implement JALRS16 instructionZoran Jovanovic2014-10-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5027 llvm-svn: 219493
* Add tests for r219479.David Majnemer2014-10-102-0/+263
| | | | llvm-svn: 219480
* SimplifyCFG: Don't convert phis into selects if we could remove undef behaviorArnold Schwaighofer2014-10-101-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead We used to transform this: define void @test6(i1 %cond, i8* %ptr) { entry: br i1 %cond, label %bb1, label %bb2 bb1: br label %bb2 bb2: %ptr.2 = phi i8* [ %ptr, %entry ], [ null, %bb1 ] store i8 2, i8* %ptr.2, align 8 ret void } into this: define void @test6(i1 %cond, i8* %ptr) { %ptr.2 = select i1 %cond, i8* null, i8* %ptr store i8 2, i8* %ptr.2, align 8 ret void } because the simplifycfg transformation into selects would happen to happen before the simplifycfg transformation that removes unreachable control flow (We have 'unreachable control flow' due to the store to null which is undefined behavior). The existing transformation that removes unreachable control flow in simplifycfg is: /// If BB has an incoming value that will always trigger undefined behavior /// (eg. null pointer dereference), remove the branch leading here. static bool removeUndefIntroducingPredecessor(BasicBlock *BB) Now we generate: define void @test6(i1 %cond, i8* %ptr) { store i8 2, i8* %ptr.2, align 8 ret void } I did not see any impact on the test-suite + externals. rdar://18596215 llvm-svn: 219462
* obj2yaml, COFF: Handle long section namesDavid Majnemer2014-10-102-0/+14
| | | | | | | | | | | | | Long section names are represented as a slash followed by a numeric ASCII string. This number is an offset into a string table. Print the appropriate entry in the string table instead of the less enlightening /4. N.B. yaml2obj already does the right thing, this test exercises both sides of the (de-)serialization. llvm-svn: 219458
* Improve sqrt estimate algorithm (fast-math)Sanjay Patel2014-10-091-9/+2
| | | | | | | | | | | | | | | | | | | This patch changes the fast-math implementation for calculating sqrt(x) from: y = 1 / (1 / sqrt(x)) to: y = x * (1 / sqrt(x)) This has 2 benefits: less code / faster code and one less estimate instruction that may lose precision. The only target that will be affected (until http://reviews.llvm.org/D5658 is approved) is PPC. The difference in codegen for PPC is 2 less flops for a single-precision sqrtf or vector sqrtf and 4 less flops for a double-precision sqrt. We also eliminate a constant load and extra register usage. Differential Revision: http://reviews.llvm.org/D5682 llvm-svn: 219445
* Fix bug in GPR to FPR moves in PPC64LE.Samuel Antao2014-10-091-0/+121
| | | | | | The current implementation of GPR->FPR register moves uses a stack slot. This mechanism writes a double word and reads a word. In big-endian the load address must be displaced by 4-bytes in order to get the right value. In little endian this is no longer required. This patch fixes the issue and adds LE regression tests to fast-isel-conversion which currently expose this problem. llvm-svn: 219441
* [Reassociate] Don't canonicalize X - undef to X + (-undef).Chad Rosier2014-10-091-0/+21
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5674 PR21205 llvm-svn: 219434
* Revert "[BasicAA] Revert "Revert r218714 - Make better use of zext and sign ↵Hal Finkel2014-10-092-88/+0
| | | | | | | | information."" This reverts commit r219135 -- still causing miscompiles in SPEC it seems... llvm-svn: 219432
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-091-0/+26
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* R600/SI: Legalize INSERT_SUBREG instructions during PostISelFoldingTom Stellard2014-10-091-0/+15
| | | | | | | | LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. llvm-svn: 219420
* [PPC64] VSX indexed-form loads use wrong instruction formatBill Schmidt2014-10-091-21/+21
| | | | | | | | | | | | | | | | | | The VSX instruction definitions for lxsdx, lxvd2x, lxvdsx, and lxvw4x incorrectly use the XForm_1 instruction format, rather than the XX1Form instruction format. This is likely a pasto when creating these instructions, which were based on lvx and so forth. This patch uses the correct format. The existing reformatting test (test/MC/PowerPC/vsx.s) missed this because the two formats differ only in that XX1Form has an extension to the target register field in bit 31. The tests for these instructions used a target register of 7, so the default of 0 in bit 31 for XForm_1 didn't expose a problem. For register numbers 32-63 this would be noticeable. I've changed the test to use higher register numbers to verify my change is effective. llvm-svn: 219416
* [InstCombine] Fix wrong folding of constant comparisons involving ashr and ↵Andrea Di Biagio2014-10-091-0/+8
| | | | | | | | | | | | | | negative values. This patch fixes a bug in method InstCombiner::FoldCmpCstShrCst where we wrongly computed the distance between the highest bits set of two negative values. This fixes PR21222. Differential Revision: http://reviews.llvm.org/D5700 llvm-svn: 219406
* [AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov2014-10-091-1/+2353
| | | | | | | Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
* [AVX512] Intrinsics for vextract*x4Adam Nemet2014-10-081-0/+36
| | | | | | | | This adds the Pat<>'s for the intrinsics. These are necessary because we don't lower these intrinsics to SDNodes but match them directly. See the rational in the previous commit. llvm-svn: 219362
* [AVX512] Add asm-only support for vextract*x4 masking variantsAdam Nemet2014-10-081-0/+8
| | | | | | | | | | | | | | | | These derive from the new asm-only masking definitions. Unfortunately I wasn't able to find a ISel pattern that we could legally generate for the masking variants. The problem is that since the destination is v4* we would need VK4 register classes and v4i1 value types to express the masking. These are however not legal types/classes in AVX512f but only in VL, so things get complicated pretty quickly. We can revisit this question later if we have a more pressing need to express something like this. So the ISel patterns are empty for the masking instructions and the next patch will add Pat<>s instead to match the intrinsics calls with instructions. llvm-svn: 219361
* [X86] Don't transform atomic-load-add into an inc/dec when inc/dec is slowRobin Morisset2014-10-081-0/+17
| | | | llvm-svn: 219357
* [X86] Avoid generating inc/dec when slow for x.atomic_store(1 + x.atomic_load())Robin Morisset2014-10-081-0/+23
| | | | | | | | | | | | | | | | | Summary: I had forgotten to check for NotSlowIncDec in the patterns that can generate inc/dec for the above pattern (added in D4796). This currently applies to Atom Silvermont, KNL and SKX. Test Plan: New checks on atomic_mi.ll Reviewers: jfb, nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5677 llvm-svn: 219336
* Inliner: Non-local functions in COMDATs shouldn't be droppedDavid Majnemer2014-10-081-0/+18
| | | | | | | | | | A function with discardable linkage cannot be discarded if its a member of a COMDAT group without considering all the other COMDAT members as well. This sort of thing is already handled by GlobalOpt/GlobalDCE. This fixes PR21206. llvm-svn: 219335
* Fix COFF section index relocation should be 16 bits, not 32Timur Iskhodzhanov2014-10-085-0/+14
| | | | | | | Original patch by Andrey Guskov! http://reviews.llvm.org/D5651 llvm-svn: 219327
* Correctly compute the size of common symbols in COFF.Rafael Espindola2014-10-081-1/+1
| | | | llvm-svn: 219324
* Print symbol sizes in this test in preparation for fixing COFF common sizes.Rafael Espindola2014-10-081-7/+7
| | | | llvm-svn: 219320
* Revert "[InstCombine] re-commit r218721 with fix for pr21199"Justin Bogner2014-10-083-153/+1
| | | | | | | | | | | | | This seems to cause a miscompile when building clang, which causes a bootstrapped clang to fail or crash in several of its tests. See: http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-RA/builds/1184 http://bb.pgr.jp/builders/clang-3stage-x86_64-linux/builds/7813 This reverts commit r219282. llvm-svn: 219317
* [AVX512] Added intrinsics for 128-, 256- and 512-bit versions of ↵Robert Khasanov2014-10-084-0/+1440
| | | | | | | | | | | VPCMP/VPCMPU{BWDQ} Added CMP_MASK_CC intrinsic type. Added tests for intrinsics. Patch by Sergey Lisitsyn <sergey.lisitsyn@intel.com> llvm-svn: 219316
* Emit unaligned access build attribute for ARMRenato Golin2014-10-081-0/+28
| | | | | | Patch by Charlie Turner. llvm-svn: 219301
* GlobalOpt: Don't drop unused memberes of a ComdatDavid Majnemer2014-10-081-0/+19
| | | | | | | | | A linkonce_odr member of a COMDAT shouldn't be dropped if we need to keep the entire COMDAT group. This fixes PR21191. llvm-svn: 219283
* [InstCombine] re-commit r218721 with fix for pr21199Gerolf Hoflehner2014-10-083-1/+153
| | | | | | | | The icmp-select-icmp optimization targets select-icmp.eq only. This is now ensured by testing the branch predicate explictly. This commit also includes the test case for pr21199. llvm-svn: 219282
* COFF: Don't oversize COMMON symbols when targeting BFD ldDavid Majnemer2014-10-081-1/+8
| | | | | | | | | | | | | | COFF normally doesn't allow us to describe the alignment of COMMON symbols. It turns out that most linkers use the symbol size as a hint as to how aligned the symbol should be. However the BFD folks have added a .drectve command, which we now support as of r219229, that allows us to specify the alignment precisely. With this in mind, stop rounding sizes up. llvm-svn: 219281
* llvm-dwarfdump: Add support for some COFF relocationsDavid Majnemer2014-10-081-1/+5
| | | | | | | DWARF in COFF utilizes several relocations. Implement support for them in RelocVisitor to support llvm-dwarfdump. llvm-svn: 219280
* [AArch64] Generate vector signed/unsigned mul and mla/mls long.Chad Rosier2014-10-081-0/+332
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5589 Patch by Balaram Makam <bmakam@codeaurora.org>!! llvm-svn: 219276
* llvm-readobj: add test for r219228Rui Ueyama2014-10-082-0/+2
| | | | llvm-svn: 219274
* Revert r219175 - [InstCombine] re-commit r218721 icmp-select-icmp optimizationHans Wennborg2014-10-081-1/+1
| | | | | | This seems to have caused PR21199. llvm-svn: 219264
* [X86] Fix a bug with fetch_add(INT32_MIN)Robin Morisset2014-10-071-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fix pr21099 The pseudocode of what we were doing (spread through two functions) was: if (operand.doesNotFitIn32Bits()) Opc.initializeWithFoo(); if (operand < 0) operand = -operand; if (operand.doesFitIn8Bits()) Opc.initializeWithBar(); else if (operand.doesFitIn32Bits()) Opc.initializeWithBlah(); doStuff(Opc); So for operand == INT32_MIN, Opc was never initialized because the operand changes from fitting in 32 bits to not fitting, causing the various bugs/error messages noted by pr21099. This patch adds an extra test at the beginning for this case, and an llvm_unreachable to have better error message if the operand ends up not fitting in 32-bits at the end. Test Plan: new test + make check Reviewers: jfb Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5655 llvm-svn: 219257
* DebugInfo+DFSan: Ensure that debug info references to llvm::Functions remain ↵David Blaikie2014-10-072-0/+38
| | | | | | | | | | | | | | | | | | | | | | pointing to the underlying function when wrappers are created This is somewhat the inverse of how similar bugs in DAE and ArgPromo manifested and were addressed. In those passes, individual call sites were visited explicitly, and then the old function was deleted. This left the debug info with a null llvm::Function* that needed to be updated to point to the new function. In the case of DFSan, it RAUWs the old function with the wrapper, which includes debug info. So now the debug info refers to the wrapper, which doesn't actually have any instructions with debug info in it, so it is ignored entirely - resulting in a DW_TAG_subprogram with no high/low pc, etc. Instead, fix up the debug info to refer to the original function after the RAUW messed it up. Reviewed/discussed with Peter Collingbourne on the llvm-dev mailing list. llvm-svn: 219249
* LoopUnroll: Create sub-loops in LoopInfoDuncan P. N. Exon Smith2014-10-071-0/+35
| | | | | | | | | | | | | `LoopUnrollPass` says that it preserves `LoopInfo` -- make it so. In particular, tell `LoopInfo` about copies of inner loops when unrolling the outer loop. Conservatively, also tell `ScalarEvolution` to forget about the original versions of these loops, since their inputs may have changed. Fixes PR20987. llvm-svn: 219241
* R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-10-071-0/+18
| | | | | | | Added a FIXME coment instead, we need to handle the case where the two DS instructions being compared have different numbers of operands. llvm-svn: 219236
* MC: add support for -aligncomm GNU extensionSaleem Abdulrasool2014-10-071-0/+50
| | | | | | | The GNU linker supports an -aligncomm directive that allows for power-of-2 alignment of common data. Add support to emit this directive. llvm-svn: 219229
* Two case switch to select optimizationMarcello Maggioni2014-10-073-3/+79
| | | | | | | | | | | | | | | | | | | | | This optimization tries to convert switch instructions that are used to select a value with only 2 unique cases + default block to a select or a couple of selects (depending if the default block is reachable or not). The typical case this optimization wants to be able to optimize is this one: Example: switch (a) { case 10: %0 = icmp eq i32 %a, 10 return 10; %1 = select i1 %0, i32 10, i32 4 case 20: ----> %2 = icmp eq i32 %a, 20 return 2; %3 = select i1 %2, i32 2, i32 %1 default: return 4; } It also sets the base for further optimizations that are planned and being reviewed. llvm-svn: 219223
* DebugInfo+DeadArgElimination: Ensure llvm::Function*s from debug info are ↵David Blaikie2014-10-071-47/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | updated even when DAE removes both varargs and non-varargs arguments on the same function. After some stellar (& inspired) help from Reid Kleckner providing a test case for some rather unstable undefined behavior showing up as assertions produced by r214761, I was able to fix this issue in DAE involving the application of both varargs removal, followed by normal argument removal. Indeed I introduced this same bug into ArgumentPromotion (r212128) by copying the code from DAE, and when I fixed the bug in ArgPromo (r213805) and commented in that patch that I didn't need to address the same issue in DAE because it was a single pass. Turns out it's two pass, one for the varargs and one for the normal arguments, so the same fix is needed (at least during varargs removal). So here it is. (the observable/net effect of this bug, even when it didn't result in assertion failure, is that debug info would describe the DAE'd function in the abstract, but wouldn't provide high/low_pc, variable locations, line table, etc (it would appear as though the function had been entirely optimized away), see the original PR14016 for details of the general problem) I'm not recommitting the assertion just yet, as there's been another regression of it since I last tried. It might just be a few test cases weren't adequately updated after Adrian or Duncan's recent schema changes. llvm-svn: 219210
* Remove Extra lines. NFC.Suyog Sarda2014-10-071-2/+0
| | | | llvm-svn: 219201
* [asan-asm-instrumentation] CFI directives are generated for .S files.Yuri Gorshenin2014-10-074-13/+80
| | | | | | | | | | | | Summary: CFI directives are generated for .S files. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5520 llvm-svn: 219199
* [mips] Return {f128} correctly for N32/N64.Daniel Sanders2014-10-071-0/+36
| | | | | | | | | | | | | | | | | Summary: According to the ABI documentation, f128 and {f128} should both be returned in $f0 and $f2. However, this doesn't match GCC's behaviour which is to return f128 in $f0 and $f2, but {f128} in $f0 and $f1. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5578 llvm-svn: 219196
* [X86] Fix a bug where the disassembler was ignoring the VEX.W bit in 32-bit ↵Craig Topper2014-10-071-0/+3
| | | | | | | | | | mode for certain instructions it shouldn't. Unfortunately, this isn't easy to fix since there's no simple way to figure out from the disassembler tables whether the W-bit is being used to select a 64-bit GPR or if its a required part of the opcode. The fix implemented here just looks for "64" in the instruction name and ignores the W-bit in 32-bit mode if its present. Fixes PR21169. llvm-svn: 219194
* GlobalDCE: Don't drop any COMDAT membersDavid Majnemer2014-10-071-0/+17
| | | | | | | | | If we require a single member of a comdat, require all of the other members as well. This fixes PR20981. llvm-svn: 219191
* gold plugin: Handle gold selecting a linkonce GV when a weak is present.Rafael Espindola2014-10-072-0/+22
| | | | | | | | | The plugin API doesn't have the notion of linkonce, only weak. It is up to the plugin to figure out if a symbol used only for the symbol table can be dropped. In particular, it has to avoid dropping a linkonce_odr selected by gold if there is also a weak_odr. llvm-svn: 219188
* [FastISel][AArch64] Teach the address computation code to also fold ↵Juergen Ributzka2014-10-071-20/+10
| | | | | | | | | | sign-/zero-extends. The code already folds sign-/zero-extends, but only if they are arguments to mul and shift instructions. This extends the code to also fold them when they are direct inputs. llvm-svn: 219187
* [FastISel][AArch64] Teach the address computation to also fold sub instructions.Juergen Ributzka2014-10-071-10/+10
| | | | | | | Tiny enhancement to the address computation code to also fold sub instructions if the rhs is constant and can be folded into the offset. llvm-svn: 219186
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