summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC
Commit message (Collapse)AuthorAgeFilesLines
* [MC] Create unique .pdata sections for every .text sectionReid Kleckner2016-05-022-5/+157
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds a unique ID to the COFF section uniquing map, similar to the one we have for ELF. The unique id is not currently exposed via the assembler because we don't have a use case for it yet. Users generally create .pdata with the .seh_* family of directives, and the assembler internally needs to produce .pdata and .xdata sections corresponding to the code section. The association between .text sections and the assembler-created .xdata and .pdata sections is maintained as an ID field of MCSectionCOFF. The CFI-related sections are created with the given unique ID, so if more code is added to the same text section, we can find and reuse the CFI sections that were already created. Reviewers: majnemer, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19376 llvm-svn: 268331
* [AVX512] VPACKUSWB/VPACKSSWB should not be encoded with EVEX.W=1. While ↵Craig Topper2016-05-012-198/+198
| | | | | | there fix the execution domain for VPACKSSDW/VPACKUSDW. llvm-svn: 268200
* [AMDGPU][llvm-mc] Add some missing testcases to trap.sArtem Tamazov2016-04-291-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D19602 llvm-svn: 268073
* Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. ↵Artem Tamazov2016-04-293-0/+108
| | | | | | | | | | | Rework M0 exclusion for SMRD." Previously reverted by r267752. r267733 review: Differential Revision: http://reviews.llvm.org/D19342 llvm-svn: 268066
* [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-4/+20
| | | | | | | | | | | | | | | Summary: This removes the temporary call to isIntegratedAssemblerRequired() which was added recently. It's effect is now acheived directly in the MipsTargetStreamer hierarchy. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19715 llvm-svn: 268058
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Make section sizes a multiple of the alignment.Daniel Sanders2016-04-291-0/+106
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19008 llvm-svn: 268036
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-294-143/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
* [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructionsZlatko Buljan2016-04-296-7/+122
| | | | | | Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
* This reverts commit r265505.Kit Barton2016-04-283-111/+0
| | | | | | | Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. llvm-svn: 267927
* [Hexagon] Add instruction aliases for vector unsigned compare-equalKrzysztof Parzyszek2016-04-281-0/+36
| | | | | | Unsigned compare-equal instructions are mapped to signed compare-equal. llvm-svn: 267925
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-281-0/+10
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-281-0/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* [Hexagon] Merging nops in to previous packet rather than always creating a ↵Colin LeMahieu2016-04-271-0/+60
| | | | | | new one. llvm-svn: 267798
* Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for ↵Chad Rosier2016-04-273-107/+0
| | | | | | | | SMRD." This reverts commit r267733 due to a -Werror,-Wunused-function error. llvm-svn: 267752
* [AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.Artem Tamazov2016-04-273-0/+107
| | | | | | | | | | | Added support of TTMP quads. Reworked M0 exclusion machinery for SMRD and similar instructions to enable usage of TTMP registers in those instructions as destinations. Tests added. Differential Revision: http://reviews.llvm.org/D19342 llvm-svn: 267733
* [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware ↵Artem Tamazov2016-04-273-22/+59
| | | | | | | | | | | | registers. Possibility to specify code of hardware register kept. Disassemble to symbolic name, if name is known. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19335 llvm-svn: 267724
* [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU ↵Zlatko Buljan2016-04-273-0/+16
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D16676 llvm-svn: 267694
* [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, ↵Zlatko Buljan2016-04-278-0/+95
| | | | | | | | SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
* Reapply: "ARM: put correct symbol index on indirect pointers in __thread_ptr.""Tim Northover2016-04-261-1/+5
| | | | | | | A latent bug in llvm-objdump used the wrong format specifier on 32-bit targets, causing the test to fail. This fixes the issue. llvm-svn: 267582
* [AMDGPU] Assembler: basic support for SDWA instructionsSam Kolton2016-04-261-0/+40
| | | | | | | | | | | | | | | Support for SDWA instructions for VOP1 and VOP2 encoding. Not done yet: - converters for support optional operands and modifiers - VOPC - sext() modifier - intrinsics - VOP2b (see vop_dpp.s) - V_MAC_F32 (see vop_dpp.s) Differential Revision: http://reviews.llvm.org/D19360 llvm-svn: 267553
* Revert "ARM: put correct symbol index on indirect pointers in __thread_ptr."Renato Golin2016-04-261-5/+1
| | | | | | This reverts commit r267488, as it broke some ARM buildbots. llvm-svn: 267541
* ARM: put correct symbol index on indirect pointers in __thread_ptr.Tim Northover2016-04-251-1/+5
| | | | | | Otherwise the linker has no idea what should be resolved. llvm-svn: 267488
* ARM: put extern __thread stubs in a special section.Tim Northover2016-04-251-0/+46
| | | | | | | The linker needs to know that the symbols are thread-local to do its job properly. llvm-svn: 267473
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-0/+9
| | | | | | Remember to svn add the new file. llvm-svn: 267435
* [Hexagon] Use llvm-mc instead of llc in an MC testcaseKrzysztof Parzyszek2016-04-251-9/+0
| | | | llvm-svn: 267434
* [mips][microMIPS] Revert commit r267137Hrvoje Varga2016-04-252-8/+0
| | | | | | Commit r267137 was the reason for failing tests in LLVM test suite. llvm-svn: 267419
* [mips][microMIPS] Revert commit r266977Zlatko Buljan2016-04-2512-111/+0
| | | | | | Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ... llvm-svn: 267418
* [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax.Artem Tamazov2016-04-253-11/+55
| | | | | | | | | | | | | Added hwreg(reg[,offset,width]) syntax. Default offset = 0, default width = 32. Possibility to specify 16-bit immediate kept. Added out-of-range checks. Disassembling is always to hwreg(...) format. Tests updated/added. Differential Revision: http://reviews.llvm.org/D19329 llvm-svn: 267410
* [Hexagon] Correctly set "Flags" in ELF headerKrzysztof Parzyszek2016-04-251-0/+9
| | | | llvm-svn: 267397
* [MC/ELF] Make the relaxation test more interesting.Davide Italiano2016-04-241-0/+2
| | | | | | Add a case where we can't relax. llvm-svn: 267308
* [MC/ELF] Implement support for GOTPCRELX/REX_GOTPCRELX.Davide Italiano2016-04-241-0/+18
| | | | | | | | | The option to control the emission of the new relocations is -relax-relocations (blatantly copied from GNU as). It can't be enabled by default because it breaks relatively recent versions of ld.bfd/ld.gold (late 2015). llvm-svn: 267307
* CodeGen: Use PLT relocations for relative references to unnamed_addr functions.Peter Collingbourne2016-04-222-5/+8
| | | | | | | | | | | | | The relative vtable ABI (PR26723) needs PLT relocations to refer to virtual functions defined in other DSOs. The unnamed_addr attribute means that the function's address is not significant, so we're allowed to substitute it with the address of a PLT entry. Also includes a bonus feature: addends for COFF image-relative references. Differential Revision: http://reviews.llvm.org/D17938 llvm-svn: 267211
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-226-26/+7
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [Hexagon] Add definitions for trap/pause instructionsKrzysztof Parzyszek2016-04-221-0/+36
| | | | | | Also add tests for other instructions from HexagonSystemInst.td. llvm-svn: 267162
* AMDGPU/SI: Add test missed in rL266865Nikolay Haustov2016-04-221-0/+55
| | | | llvm-svn: 267144
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-222-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-222-0/+9
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-226-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* MachO: enable .data_region directives everywhereTim Northover2016-04-213-107/+96
| | | | | | | | | | We'd disabled them on x86 because back in the early days some host tools couldn't handle the new load commands. This no longer holds: anyone capable of deploying Clang should be able to deploy its copies of ar/ranlib/etc. rdar://25254790 llvm-svn: 267075
* [Hexagon] Properly recognize register alt namesKrzysztof Parzyszek2016-04-211-0/+14
| | | | llvm-svn: 267038
* [mips][microMIPS] Implement ldpc instructionZoran Jovanovic2016-04-212-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D15009 llvm-svn: 266990
* [mips][microMIPS] Add R_MICROMIPS_PC19_S2 relocationZoran Jovanovic2016-04-212-1/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D14915 llvm-svn: 266988
* [mips][microMIPS] Add R_MICROMIPS_PC26_S1 relocationZoran Jovanovic2016-04-212-0/+47
| | | | | | Differential Revision: http://reviews.llvm.org/D14822 llvm-svn: 266985
* [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructionsZlatko Buljan2016-04-216-0/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D18855 llvm-svn: 266980
* [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL ↵Zlatko Buljan2016-04-2112-0/+111
| | | | | | | | instructions and add tests for LWM32 and SWM32 Differential Revision: http://reviews.llvm.org/D19150 llvm-svn: 266977
* [Hexagon] Fix handling of lcomm directiveKrzysztof Parzyszek2016-04-201-0/+19
| | | | | | Patch by Colin LeMahieu. llvm-svn: 266882
* [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructionsZoran Jovanovic2016-04-202-0/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D14206 llvm-svn: 266873
* AMDGPU/SI: Assembler: improvements to support trap handlers.Nikolay Haustov2016-04-201-0/+16
| | | | | | | | | | | | Add ParseAMDGPURegister which can be invoked recursively for parsing lists. Rename getRegForName to getSpecialRegForName. Support legacy SP3 register list syntax: [s2,s3,s4,s5] or [flat_scratch_lo,flat_scratch_hi]. Add 64-bit registers TBA, TMA where missing. Add some tests. Differential Revision: http://reviews.llvm.org/D19163 llvm-svn: 266865
* [mips][microMIPS]Implement CFC*, CTC* and LDC* instructionsHrvoje Varga2016-04-206-7/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D18640 llvm-svn: 266861
OpenPOWER on IntegriCloud