[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions

Differential Revision: http://reviews.llvm.org/D17989

llvm-svn: 267693

8 files changed, 95 insertions, 0 deletions

diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
index 8f25c710370..a25fc541c33 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt
@@ -292,3 +292,8 @@
 0x00 0x04 0x39 0x7c # CHECK: evp $4
 0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
 0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
index b7a84ebab6b..5934fd9214d 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
@@ -226,3 +226,9 @@
 0x00 0x04 0x39 0x7c # CHECK: evp $4
 0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
 0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
+0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
diff --git a/llvm/test/MC/Mips/micromips-shift-instructions.s b/llvm/test/MC/Mips/micromips-shift-instructions.s
index bbb71ac7208..52b71e22aac 100644
--- a/llvm/test/MC/Mips/micromips-shift-instructions.s
+++ b/llvm/test/MC/Mips/micromips-shift-instructions.s
@@ -15,6 +15,15 @@
 # CHECK-EL: srlv   $2, $3, $5     # encoding: [0x65,0x00,0x50,0x10]
 # CHECK-EL: rotr   $9, $6, 7      # encoding: [0x26,0x01,0xc0,0x38]
 # CHECK-EL: rotrv  $9, $6, $7     # encoding: [0xc7,0x00,0xd0,0x48]
+# CHECK-EL: sllv   $2, $3, $5     # encoding: [0x65,0x00,0x10,0x10]
+# CHECK-EL: srav   $2, $3, $5     # encoding: [0x65,0x00,0x90,0x10]
+# CHECK-EL: srlv   $2, $3, $5     # encoding: [0x65,0x00,0x50,0x10]
+# CHECK-EL: sllv   $2, $2, $3     # encoding: [0x43,0x00,0x10,0x10]
+# CHECK-EL: srav   $2, $2, $3     # encoding: [0x43,0x00,0x90,0x10]
+# CHECK-EL: srlv   $2, $2, $3     # encoding: [0x43,0x00,0x50,0x10]
+# CHECK-EL: sll    $3, $3, 7      # encoding: [0x63,0x00,0x00,0x38]
+# CHECK-EL: sra    $3, $3, 7      # encoding: [0x63,0x00,0x80,0x38]
+# CHECK-EL: srl    $3, $3, 7      # encoding: [0x63,0x00,0x40,0x38]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
@@ -26,6 +35,15 @@
 # CHECK-EB: srlv  $2, $3, $5      # encoding: [0x00,0x65,0x10,0x50]
 # CHECK-EB: rotr  $9, $6, 7       # encoding: [0x01,0x26,0x38,0xc0]
 # CHECK-EB: rotrv $9, $6, $7      # encoding: [0x00,0xc7,0x48,0xd0]
+# CHECK-EB: sllv $2, $3, $5       # encoding: [0x00,0x65,0x10,0x10]
+# CHECK-EB: srav $2, $3, $5       # encoding: [0x00,0x65,0x10,0x90]
+# CHECK-EB: srlv $2, $3, $5       # encoding: [0x00,0x65,0x10,0x50]
+# CHECK-EB: sllv $2, $2, $3       # encoding: [0x00,0x43,0x10,0x10]
+# CHECK-EB: srav $2, $2, $3       # encoding: [0x00,0x43,0x10,0x90]
+# CHECK-EB: srlv $2, $2, $3       # encoding: [0x00,0x43,0x10,0x50]
+# CHECK-EB: sll $3, $3, 7         # encoding: [0x00,0x63,0x38,0x00]
+# CHECK-EB: sra $3, $3, 7         # encoding: [0x00,0x63,0x38,0x80]
+# CHECK-EB: srl $3, $3, 7         # encoding: [0x00,0x63,0x38,0x40]
      sll    $4, $3, 7
      sllv   $2, $3, $5
      sra    $4, $3, 7
@@ -34,3 +52,12 @@
      srlv   $2, $3, $5
      rotr   $9, $6, 7
      rotrv  $9, $6, $7
+     sll    $2, $3, $5
+     sra    $2, $3, $5
+     srl    $2, $3, $5
+     sll    $2, $3
+     sra    $2, $3
+     srl    $2, $3
+     sll    $3, 7
+     sra    $3, 7
+     srl    $3, 7
diff --git a/llvm/test/MC/Mips/micromips/invalid.s b/llvm/test/MC/Mips/micromips/invalid.s
index 1141c1886b3..9e9894f5dc2 100644
--- a/llvm/test/MC/Mips/micromips/invalid.s
+++ b/llvm/test/MC/Mips/micromips/invalid.s
@@ -52,3 +52,8 @@
   sync 32             # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
   swe $2, -513($gp)   # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
   swe $2, 512($gp)    # CHECK: :[[@LINE]]:11: error: expected memory with $gp and 9-bit signed offset
+  sll $3, -1          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sll $3, 32          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, -1          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, 32          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, -1          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s
index 7283ca18e2d..0c22e3f2e1d 100644
--- a/llvm/test/MC/Mips/micromips32r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid.s
@@ -139,3 +139,15 @@
   evp $4, 5                # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   jalrc.hb $31             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   jalrc.hb $31, $31        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  sll $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sll $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s
index c67ee11b13f..e6142e05d69 100644
--- a/llvm/test/MC/Mips/micromips32r6/valid.s
+++ b/llvm/test/MC/Mips/micromips32r6/valid.s
@@ -291,3 +291,17 @@
   evp $4                   # CHECK: evp $4                 # encoding: [0x00,0x04,0x39,0x7c]
   jalrc.hb $4              # CHECK: jalrc.hb $4            # encoding: [0x03,0xe4,0x1f,0x3c]
   jalrc.hb $4, $5          # CHECK: jalrc.hb $4, $5        # encoding: [0x00,0x85,0x1f,0x3c]
+  sllv $2, $3, $5          # CHECK: sllv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x10]
+  sra $4, $3, 7            # CHECK: sra $4, $3, 7          # encoding: [0x00,0x83,0x38,0x80]
+  srav $2, $3, $5          # CHECK: srav $2, $3, $5        # encoding: [0x00,0x65,0x10,0x90]
+  srl $4, $3, 7            # CHECK: srl $4, $3, 7          # encoding: [0x00,0x83,0x38,0x40]
+  srlv $2, $3, $5          # CHECK: srlv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x50]
+  sll $2, $3, $5           # CHECK: sllv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x10]
+  sra $2, $3, $5           # CHECK: srav $2, $3, $5        # encoding: [0x00,0x65,0x10,0x90]
+  srl $2, $3, $5           # CHECK: srlv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x50]
+  sll $2, $3               # CHECK: sllv $2, $2, $3        # encoding: [0x00,0x43,0x10,0x10]
+  sra $2, $3               # CHECK: srav $2, $2, $3        # encoding: [0x00,0x43,0x10,0x90]
+  srl $2, $3               # CHECK: srlv $2, $2, $3        # encoding: [0x00,0x43,0x10,0x50]
+  sll $3, 7                # CHECK: sll $3, $3, 7          # encoding: [0x00,0x63,0x38,0x00]
+  sra $3, 7                # CHECK: sra $3, $3, 7          # encoding: [0x00,0x63,0x38,0x80]
+  srl $3, 7                # CHECK: srl $3, $3, 7          # encoding: [0x00,0x63,0x38,0x40]
diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s
index a6efc52ae95..7ef48b21a11 100644
--- a/llvm/test/MC/Mips/micromips64r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips64r6/invalid.s
@@ -164,3 +164,15 @@
   evp $4, 5                    # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
   jalrc.hb $31                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
   jalrc.hb $31, $31            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
+  sll $4, $3, -1               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $4, $3, 32               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, -1               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, 32               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, -1               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, 32               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sll $3, 32                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, 32                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, 32                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s
index 8cdc448405e..d1649dde0ee 100644
--- a/llvm/test/MC/Mips/micromips64r6/valid.s
+++ b/llvm/test/MC/Mips/micromips64r6/valid.s
@@ -209,5 +209,19 @@ a:
         evp $4                   # CHECK: evp $4                  # encoding: [0x00,0x04,0x39,0x7c]
         jalrc.hb $4              # CHECK: jalrc.hb $4             # encoding: [0x03,0xe4,0x1f,0x3c]
         jalrc.hb $4, $5          # CHECK: jalrc.hb $4, $5         # encoding: [0x00,0x85,0x1f,0x3c]
+        sllv $2, $3, $5          # CHECK: sllv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x10]
+        sra $4, $3, 7            # CHECK: sra $4, $3, 7           # encoding: [0x00,0x83,0x38,0x80]
+        srav $2, $3, $5          # CHECK: srav $2, $3, $5         # encoding: [0x00,0x65,0x10,0x90]
+        srl $4, $3, 7            # CHECK: srl $4, $3, 7           # encoding: [0x00,0x83,0x38,0x40]
+        srlv $2, $3, $5          # CHECK: srlv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x50]
+        sll $2, $3, $5           # CHECK: sllv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x10]
+        sra $2, $3, $5           # CHECK: srav $2, $3, $5         # encoding: [0x00,0x65,0x10,0x90]
+        srl $2, $3, $5           # CHECK: srlv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x50]
+        sll $2, $3               # CHECK: sllv $2, $2, $3         # encoding: [0x00,0x43,0x10,0x10]
+        sra $2, $3               # CHECK: srav $2, $2, $3         # encoding: [0x00,0x43,0x10,0x90]
+        srl $2, $3               # CHECK: srlv $2, $2, $3         # encoding: [0x00,0x43,0x10,0x50]
+        sll $3, 7                # CHECK: sll $3, $3, 7           # encoding: [0x00,0x63,0x38,0x00]
+        sra $3, 7                # CHECK: sra $3, $3, 7           # encoding: [0x00,0x63,0x38,0x80]
+        srl $3, 7                # CHECK: srl $3, $3, 7           # encoding: [0x00,0x63,0x38,0x40]
 
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