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| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-04-27 11:31:44 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-04-27 11:31:44 +0000 |
| commit | de0bbe6d1cf2f9273c54b3b35c1f07ea61ca079f (patch) | |
| tree | df945930f4257abd884e7ef97bb6c55556147fe7 /llvm/test/MC | |
| parent | 29813620bc88730f9011c2a0243edde34acfb001 (diff) | |
| download | bcm5719-llvm-de0bbe6d1cf2f9273c54b3b35c1f07ea61ca079f.tar.gz bcm5719-llvm-de0bbe6d1cf2f9273c54b3b35c1f07ea61ca079f.zip | |
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions
Differential Revision: http://reviews.llvm.org/D16676
llvm-svn: 267694
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/invalid.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/valid.s | 6 |
3 files changed, 16 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 5934fd9214d..c46f7de2012 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -232,3 +232,9 @@ 0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 +0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3 +0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15 +0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15 +0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10 +0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11 +0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5 diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index 7ef48b21a11..2d0c3a21d4c 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -176,3 +176,7 @@ sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate + dneg $7, 5 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction + dneg 4 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + dnegu $1, 3 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction + dnegu 7 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index d1649dde0ee..fe8bc3607c0 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -223,5 +223,11 @@ a: sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00] sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] + dsub $1, $2, $3 # CHECK: dsub $1, $2, $3 # encoding: [0x58,0x62,0x09,0x90] + dsubu $3, $7, $15 # CHECK: dsubu $3, $7, $15 # encoding: [0x59,0xe7,0x19,0xd0] + dneg $7, $15 # CHECK: dneg $7, $15 # encoding: [0x59,0xe0,0x39,0x90] + dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90] + dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0] + dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0] 1: |
