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| author | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-04-22 06:44:34 +0000 |
|---|---|---|
| committer | Zlatko Buljan <Zlatko.Buljan@imgtec.com> | 2016-04-22 06:44:34 +0000 |
| commit | ae720dbbb61f8dcfe8bf44ec01160183c07cf40e (patch) | |
| tree | db19c3da3152aa6d1e4d46bbcf257b359c62c1e3 /llvm/test/MC | |
| parent | d0ce8f1485e0bf6ed850926216bd34cec4e57c08 (diff) | |
| download | bcm5719-llvm-ae720dbbb61f8dcfe8bf44ec01160183c07cf40e.tar.gz bcm5719-llvm-ae720dbbb61f8dcfe8bf44ec01160183c07cf40e.zip | |
[mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions
Differential Revision: http://reviews.llvm.org/D18687
llvm-svn: 267114
Diffstat (limited to 'llvm/test/MC')
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/invalid.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips32r6/valid.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/invalid.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Mips/micromips64r6/valid.s | 6 |
6 files changed, 36 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index 955dc4d2ab1..feaf26dce90 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -302,3 +302,9 @@ 0x00 0x00 0x13 0x7c # CHECK: tlbr 0x00 0x00 0x23 0x7c # CHECK: tlbwi 0x00 0x00 0x33 0x7c # CHECK: tlbwr +0x00 0x00 0x19 0x7c # CHECK: dvp +0x00 0x04 0x19 0x7c # CHECK: dvp $4 +0x00 0x00 0x39 0x7c # CHECK: evp +0x00 0x04 0x39 0x7c # CHECK: evp $4 +0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4 +0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index e5aef3266a1..f53747878a1 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -230,3 +230,9 @@ 0x00 0x00 0x13 0x7c # CHECK: tlbr 0x00 0x00 0x23 0x7c # CHECK: tlbwi 0x00 0x00 0x33 0x7c # CHECK: tlbwr +0x00 0x00 0x19 0x7c # CHECK: dvp +0x00 0x04 0x19 0x7c # CHECK: dvp $4 +0x00 0x00 0x39 0x7c # CHECK: evp +0x00 0x04 0x39 0x7c # CHECK: evp $4 +0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4 +0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index 24e5a14d60c..1cbf251c0f0 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -149,3 +149,9 @@ tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index 63ec604d578..5223e9abdc0 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -313,3 +313,9 @@ tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] + dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] + dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] + evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] + evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c] + jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c] + jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c] diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index 42f31513429..c76f1d396fa 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -174,3 +174,9 @@ tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction + evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction + jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different + jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index 8ec7f8587dd..cf4eaf1308b 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -225,5 +225,11 @@ a: tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c] tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c] tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c] + dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c] + dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c] + evp # CHECK: evp $zero # encoding: [0x00,0x00,0x39,0x7c] + evp $4 # CHECK: evp $4 # encoding: [0x00,0x04,0x39,0x7c] + jalrc.hb $4 # CHECK: jalrc.hb $4 # encoding: [0x03,0xe4,0x1f,0x3c] + jalrc.hb $4, $5 # CHECK: jalrc.hb $4, $5 # encoding: [0x00,0x85,0x1f,0x3c] 1: |
