| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Improve assembler missing feature warnings | Simon Cook | 2019-12-10 | 1 | -4/+4 |
| * | [RISCV] Add support for RVC HINT instructions | Luis Marques | 2019-08-21 | 1 | -8/+9 |
| * | [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand types | Ana Pazos | 2018-09-13 | 1 | -0/+9 |
| * | [RISCV] Implement c.lui immediate operand constraint | Shiva Chen | 2018-02-22 | 1 | -3/+5 |
| * | [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zero | Shiva Chen | 2018-02-02 | 1 | -4/+9 |
| * | [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlen... | Alex Bradbury | 2017-12-15 | 1 | -1/+1 |
| * | [RISCV] MC layer support for the remaining RVC instructions | Alex Bradbury | 2017-12-13 | 1 | -0/+45 |
| * | [RISCV] MC layer support for the jump/branch instructions of the RVC extension | Alex Bradbury | 2017-12-07 | 1 | -0/+13 |
| * | [RISCV] MC layer support for load/store instructions of the C (compressed) ex... | Alex Bradbury | 2017-12-07 | 1 | -0/+18 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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