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* [RISCV] Improve assembler missing feature warningsSimon Cook2019-12-101-4/+4
| | | | | | | | This adds support for printing improved missing feature error messages from the assembler, which now indicates which feature caused the parse to fail. Differential Revision: https://reviews.llvm.org/D69899
* [RISCV] Add support for RVC HINT instructionsLuis Marques2019-08-211-8/+9
| | | | | | | | | The hint instructions are enabled by default (if the standard C extension is enabled). To disable them pass -mattr=-rvc-hints. Differential Revision: https://reviews.llvm.org/D62592 llvm-svn: 369528
* [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand typesAna Pazos2018-09-131-0/+9
| | | | | | | | | | | | | | | | | | | | Summary: Fixed assertions due to invalid fixup when encoding compressed instructions (c.addi, c.addiw, c.li, c.andi) with bare symbols with/without modifiers. This matches GAS behavior as well. This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D52005 llvm-svn: 342160
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-221-3/+5
| | | | | | | | | | | | Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff]. The RISC-V ISA describes the constraint as [1, 63], with that value being loaded in to bits 17-12 of the destination register and sign extended from bit 17. Therefore, this 6-bit immediate can represent values in the ranges [1, 31] and [0xfffe0, 0xfffff]. Differential Revision: https://reviews.llvm.org/D42834 llvm-svn: 325792
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-021-4/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D42782 llvm-svn: 324055
* [RISCV] Change shift amount operand of RVC shift instructions to ↵Alex Bradbury2017-12-151-1/+1
| | | | | | | | | | | | | | uimmlog2xlennonzero c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. llvm-svn: 320799
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-131-0/+45
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+13
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
* [RISCV] MC layer support for load/store instructions of the C (compressed) ↵Alex Bradbury2017-12-071-0/+18
extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
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