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* Revert r328975, it makes TableGen assert on the bots.Nico Weber2018-04-021-192/+0
* [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructionsDmitry Preobrazhensky2018-04-021-0/+192
* [AMDGPU][MC] Added ds_add_src2_f32Dmitry Preobrazhensky2018-03-281-0/+3
* [AMDGPU][MC] Added PCK variants of image load/store instructionsDmitry Preobrazhensky2018-03-281-0/+28
* [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_xDmitry Preobrazhensky2018-03-281-0/+22
* [AMDGPU][MC][GFX9] Added s_scratch* instructionsDmitry Preobrazhensky2018-03-281-0/+28
* [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP o...Dmitry Preobrazhensky2018-03-161-16/+16
* [AMDGPU][MC] Corrected default values for unused SDWA operandsDmitry Preobrazhensky2018-03-164-16667/+38393
* [mips] Add support for CRC ASEPetar Jovanovic2018-03-144-0/+40
* [mips] Fix the definitions of the EVA instructionsSimon Dardis2018-03-133-3/+3
* [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD InstructionDmitry Preobrazhensky2018-03-121-0/+9
* [AMDGPU][MC] Corrected GATHER4 opcodesDmitry Preobrazhensky2018-03-121-0/+31
* [ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath2018-03-061-4/+4
* [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9.Stefan Pintilie2018-02-231-15/+0
* [AMDGPU][MC] Added lds support for MUBUF instructionsDmitry Preobrazhensky2018-02-211-0/+43
* [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168)Simon Pilgrim2018-02-171-0/+3
* [X86][3DNOW] Teach decoder about AMD 3DNow! instrsRafael Auler2018-02-151-0/+76
* [X86] Don't swap argument on BOUND instruction in at&t syntax.Craig Topper2018-02-141-2/+2
* [ARM] Re-commit r324600 with fixed LLVMBuild.txtOliver Stannard2018-02-082-2/+33
* Revert r324600 as it breaks a buildbotOliver Stannard2018-02-082-33/+2
* [ARM] Fix disassembly of invalid banked register movesOliver Stannard2018-02-082-2/+33
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-0812-0/+140
* [AArch64] Fix spelling of ICH_ELRSR_EL2 system registerOliver Stannard2018-02-061-1/+1
* [ARM][AArch64] Add CSDB speculation barrier instructionOliver Stannard2018-02-063-0/+12
* [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifierDmitry Preobrazhensky2018-02-051-1/+49
* [ARM] Add support for unpredictable MVN instructions.Yvan Roux2018-02-011-0/+38
* AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace.Changpeng Fang2018-01-302-0/+100
* [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16Dmitry Preobrazhensky2018-01-291-0/+6
* [AMDGPU][MC] Added support of 64-bit image atomicsDmitry Preobrazhensky2018-01-261-0/+32
* [AMDGPU][MC] Enabled disassembler for image atomic operationsDmitry Preobrazhensky2018-01-261-0/+32
* [mips] Properly select abs and sqrt instructionsStefan Maksimovic2018-01-2312-0/+78
* [AMDGPU][MC][GFX9] Enable inline constants for SDWA operandsDmitry Preobrazhensky2018-01-171-0/+100
* [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics.Craig Topper2018-01-121-2/+2
* [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK supportDmitry Preobrazhensky2018-01-102-1/+16
* [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'mo...Craig Topper2018-01-051-4/+4
* [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiersDmitry Preobrazhensky2017-12-291-0/+12
* [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32Dmitry Preobrazhensky2017-12-221-0/+3
* [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registersDmitry Preobrazhensky2017-12-222-0/+48
* [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling f...Craig Topper2017-12-221-0/+3
* [ARM] Armv8-R DFB instructionSam Parker2017-12-212-0/+12
* [AArch64] CCSIDR2 system registerSam Parker2017-12-201-0/+3
* AMDGPU: Partially fix disassembly of MIMG instructionsMatt Arsenault2017-12-131-0/+39
* [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tmaDmitry Preobrazhensky2017-12-112-0/+118
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-324/+0
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-101-0/+34
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-084-4/+4
* [ARC] Add instruction subset for the ARC backend.Tatyana Krasnukha2017-12-023-0/+394
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-271-0/+85
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-241-0/+36
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-221-2/+2
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