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| author | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-01-23 10:09:39 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-01-23 10:09:39 +0000 |
| commit | 98749e0249892886dcbdf1c972b762660dc09029 (patch) | |
| tree | debaae0bad82fba699608af77ee2153791e45565 /llvm/test/MC/Disassembler | |
| parent | 007b425b776a50b3b8d3caa482bb8ca96c48a80d (diff) | |
| download | bcm5719-llvm-98749e0249892886dcbdf1c972b762660dc09029.tar.gz bcm5719-llvm-98749e0249892886dcbdf1c972b762660dc09029.zip | |
[mips] Properly select abs and sqrt instructions
- Alter abs for micromips to have both AFGR64 and FGR64
variants, same as sqrt
- Remove sqrt and abs from MicroMips32r6InstrInfo.td,
use micromips FGR64 variants
- Restrict non-micromips abs/sqrt with NotInMicroMips
predicate
Differential revision: https://reviews.llvm.org/D41439
llvm-svn: 323184
Diffstat (limited to 'llvm/test/MC/Disassembler')
12 files changed, 78 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt index 0cd74f5ba71..c9e8179f642 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt @@ -204,3 +204,7 @@ 0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30 0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28 0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8 +0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12 +0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12 +0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12 +0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt new file mode 100644 index 00000000000..65525acee13 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \ +# RUN: | FileCheck %s + +0x0c 0x54 0x3b 0x0a # CHECK: sqrt.s $f0, $f12 +0x0c 0x54 0x7b 0x03 # CHECK: abs.s $f0, $f12 +0x0c 0x54 0x3b 0x4a # CHECK: sqrt.d $f0, $f12 +0x0c 0x54 0x7b 0x23 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt new file mode 100644 index 00000000000..cd2265838c8 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 %s \ +# RUN: | FileCheck %s + +0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12 +0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12 +0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12 +0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt index dbab070b874..560647bf2bf 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt @@ -208,3 +208,7 @@ 0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30 0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28 0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8 +0x54 0x0c 0x0a 0x3b # CHECK: sqrt.s $f0, $f12 +0x54 0x0c 0x03 0x7b # CHECK: abs.s $f0, $f12 +0x54 0x0c 0x4a 0x3b # CHECK: sqrt.d $f0, $f12 +0x54 0x0c 0x23 0x7b # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt new file mode 100644 index 00000000000..0e46c7245aa --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64-el.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 +0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 +0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 +0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt new file mode 100644 index 00000000000..1c72fcabb09 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-fp64.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 +0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 +0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 +0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt new file mode 100644 index 00000000000..80eaa5b11f9 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64-el.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r2 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 +0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 +0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 +0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt new file mode 100644 index 00000000000..56de5c78b36 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-fp64.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r2 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 +0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 +0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 +0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt new file mode 100644 index 00000000000..15282ab50e0 --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64-el.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r3 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 +0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 +0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 +0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt new file mode 100644 index 00000000000..5b9519ec23c --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-fp64.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r3 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 +0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 +0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 +0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt new file mode 100644 index 00000000000..478a7f2c4cc --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64-el.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mipsel -mcpu=mips32r5 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x04 0x60 0x00 0x46 # CHECK: sqrt.s $f0, $f12 +0x05 0x60 0x00 0x46 # CHECK: abs.s $f0, $f12 +0x04 0x60 0x20 0x46 # CHECK: sqrt.d $f0, $f12 +0x05 0x60 0x20 0x46 # CHECK: abs.d $f0, $f12 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt new file mode 100644 index 00000000000..239dd4be7aa --- /dev/null +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-fp64.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble -arch=mips -mcpu=mips32r5 -mattr=+fp64 %s | \ +# RUN: FileCheck %s + +0x46 0x00 0x60 0x04 # CHECK: sqrt.s $f0, $f12 +0x46 0x00 0x60 0x05 # CHECK: abs.s $f0, $f12 +0x46 0x20 0x60 0x04 # CHECK: sqrt.d $f0, $f12 +0x46 0x20 0x60 0x05 # CHECK: abs.d $f0, $f12 |
