| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | AMDGPU/SI: Assembler: Unify parsing/printing of operands. | Nikolay Haustov | 2016-04-29 | 1 | -34/+34 |
| * | This reverts commit r265505. | Kit Barton | 2016-04-28 | 1 | -44/+0 |
| * | [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware regis... | Artem Tamazov | 2016-04-27 | 1 | -3/+9 |
| * | [mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU i... | Zlatko Buljan | 2016-04-27 | 1 | -0/+6 |
| * | [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV,... | Zlatko Buljan | 2016-04-27 | 2 | -0/+11 |
| * | [mips][microMIPS] Revert commit r267137 | Hrvoje Varga | 2016-04-25 | 1 | -4/+0 |
| * | [mips][microMIPS] Revert commit r266977 | Zlatko Buljan | 2016-04-25 | 4 | -24/+0 |
| * | [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax. | Artem Tamazov | 2016-04-25 | 1 | -5/+5 |
| * | [mips][microMIPS] Revert commit r266861. | Zoran Jovanovic | 2016-04-22 | 1 | -6/+0 |
| * | [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions | Hrvoje Varga | 2016-04-22 | 1 | -0/+4 |
| * | [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions | Zlatko Buljan | 2016-04-22 | 2 | -0/+12 |
| * | [mips][microMIPS] Implement ldpc instruction | Zoran Jovanovic | 2016-04-21 | 1 | -0/+1 |
| * | [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions | Zlatko Buljan | 2016-04-21 | 2 | -0/+8 |
| * | [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructio... | Zlatko Buljan | 2016-04-21 | 4 | -0/+24 |
| * | [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions | Zoran Jovanovic | 2016-04-20 | 1 | -0/+6 |
| * | [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions | Hrvoje Varga | 2016-04-20 | 1 | -0/+6 |
| * | [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC. | Mandeep Singh Grang | 2016-04-19 | 1 | -1/+1 |
| * | [AMDGPU][llvm-mc] s_setreg* - Fix order of operands | Artem Tamazov | 2016-04-18 | 1 | -2/+2 |
| * | Summary: | Simon Dardis | 2016-04-14 | 4 | -0/+8 |
| * | [PowerPC] Basic support for P9 byte comparison and count trailing zero insns | Nemanja Ivanovic | 2016-04-13 | 1 | -0/+18 |
| * | [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, D... | Zlatko Buljan | 2016-04-13 | 1 | -4/+4 |
| * | Revert "[mips] MIPSR6 Compact branch aliases" | Simon Dardis | 2016-04-12 | 4 | -8/+0 |
| * | [mips] MIPSR6 Compact branch aliases | Simon Dardis | 2016-04-12 | 4 | -0/+8 |
| * | [SystemZ] Add SVC instruction | Ulrich Weigand | 2016-04-11 | 1 | -0/+12 |
| * | [mips][microMIPS] Add CodeGen support for ADD, ADDIU*, ADDU* and DADD* instru... | Zlatko Buljan | 2016-04-08 | 1 | -0/+22 |
| * | [AMDGPU] Add some VI disassembler tests missing from previous autogeneration ... | Valery Pykhtin | 2016-04-08 | 1 | -0/+66 |
| * | [AMDGPU] fix readlane/readfirstlane src vgpr operand type. | Valery Pykhtin | 2016-04-07 | 2 | -2/+5 |
| * | [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random nu... | Chuang-Yu Cheng | 2016-04-06 | 1 | -0/+44 |
| * | [Power9] Implement copy-paste, msgsync, slb, and stop instructions | Chuang-Yu Cheng | 2016-04-06 | 1 | -0/+21 |
| * | [SystemZ] Add compare-and-branch instructions to MC | Ulrich Weigand | 2016-04-04 | 1 | -0/+552 |
| * | [mips][microMIPS] Revert commits r264245 and r264248. | Zoran Jovanovic | 2016-04-02 | 1 | -4/+4 |
| * | [AMDGPU] fix MADAK/MADMK instructions operand namings to match encoding fields. | Valery Pykhtin | 2016-04-01 | 1 | -8/+8 |
| * | [PPC] basic support for Power 9 direct move instructions | Ehsan Amiri | 2016-03-31 | 1 | -0/+9 |
| * | [AMDGPU] enable few disassembler tests that were mistakenly marked as FIXME. | Valery Pykhtin | 2016-03-31 | 1 | -8/+8 |
| * | [PowerPC] Basic support for P9 atomic loads and stores | Nemanja Ivanovic | 2016-03-31 | 2 | -0/+19 |
| * | [AMDGPU] Disassembler: support for DPP | Sam Kolton | 2016-03-31 | 1 | -0/+89 |
| * | [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions | Zlatko Buljan | 2016-03-31 | 2 | -0/+12 |
| * | [lanai] Add Lanai backend. | Jacques Pienaar | 2016-03-28 | 2 | -0/+765 |
| * | [Power9] Implement new altivec instructions: bcd* series | Chuang-Yu Cheng | 2016-03-28 | 1 | -0/+39 |
| * | [Power9] Implement new vsx instructions: insert, extract, test data class, mi... | Chuang-Yu Cheng | 2016-03-28 | 1 | -0/+93 |
| * | [Power9] Implement new vsx instructions: quad-precision move, fp-arithmetic | Chuang-Yu Cheng | 2016-03-28 | 1 | -0/+66 |
| * | [Power9] Implement new altivec instructions: permute, count zero, extend sign... | Chuang-Yu Cheng | 2016-03-26 | 1 | -0/+85 |
| * | [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, D... | Zlatko Buljan | 2016-03-24 | 1 | -4/+4 |
| * | [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions | Hrvoje Varga | 2016-03-24 | 2 | -0/+25 |
| * | [AMDGPU] Fix missing assembler predicates. | Valery Pykhtin | 2016-03-23 | 1 | -0/+236 |
| * | [AMDGPU] add VI disassembler tests. NFC. | Valery Pykhtin | 2016-03-17 | 13 | -3/+1700 |
| * | [AMDGPU] Fix VOPC instruction operand namings | Valery Pykhtin | 2016-03-11 | 1 | -0/+25 |
| * | [AMDGPU] Fix SMEM instructions encoding/operand namings | Valery Pykhtin | 2016-03-10 | 1 | -0/+40 |
| * | This change adds co-processor condition branching and conditional traps to th... | Chris Dewhurst | 2016-03-09 | 2 | -2/+218 |
| * | [Power9] Implement new vsx instructions: load, store instructions for vector ... | Kit Barton | 2016-03-08 | 1 | -0/+75 |
