| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Reduce verbiage of lit.local.cfg files | Alp Toker | 2014-06-09 | 1 | -2/+1 |
| | | | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496 | ||||
| * | [tests] Cleanup initialization of test suffixes. | Daniel Dunbar | 2013-08-16 | 1 | -2/+0 |
| | | | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513 | ||||
| * | [XCore] Add LDAPB instructions. | Richard Osborne | 2013-05-05 | 1 | -0/+6 |
| | | | | | | | | With the change the disassembler now supports the XCore ISA in its entirety. llvm-svn: 181155 | ||||
| * | [XCore] Add BLRB instructions. | Richard Osborne | 2013-05-05 | 1 | -0/+6 |
| | | | | | llvm-svn: 181152 | ||||
| * | Use object file specific section type for initial text section | Nico Rieck | 2013-04-14 | 1 | -1/+0 |
| | | | | | llvm-svn: 179494 | ||||
| * | [XCore] Add bru instruction. | Richard Osborne | 2013-04-04 | 1 | -0/+3 |
| | | | | | llvm-svn: 178783 | ||||
| * | [XCore] The RRegs register class is a superset of GRRegs. | Richard Osborne | 2013-04-04 | 1 | -0/+48 |
| | | | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. llvm-svn: 178782 | ||||
| * | [XCore] Check disassembly of the st8 instruction. | Richard Osborne | 2013-04-03 | 1 | -0/+3 |
| | | | | | llvm-svn: 178689 | ||||
| * | [XCore] Update disassembler test to improve coverage of the instructions. | Richard Osborne | 2013-04-03 | 1 | -6/+6 |
| | | | | | | | | Previously some instructions were unintentionally covered twice and others were not covered at all. llvm-svn: 178688 | ||||
| * | [XCore] Add missing 2r instructions. | Richard Osborne | 2013-02-17 | 1 | -0/+9 |
| | | | | | | | | These instructions are not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175407 | ||||
| * | [XCore] Add TSETR instruction. | Richard Osborne | 2013-02-17 | 1 | -0/+3 |
| | | | | | | | | This instruction is not targeted by the compiler but it is needed for the MC layer. llvm-svn: 175406 | ||||
| * | [XCore] Add missing u10 / lu10 instructions. | Richard Osborne | 2013-02-17 | 1 | -0/+12 |
| | | | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175404 | ||||
| * | [XCore] Add missing u6 / lu6 instructions. | Richard Osborne | 2013-02-17 | 1 | -0/+36 |
| | | | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175403 | ||||
| * | [XCore] Add missing l2rus instructions. | Richard Osborne | 2013-01-27 | 1 | -0/+6 |
| | | | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173634 | ||||
| * | [XCore] Add missing l2r instructions. | Richard Osborne | 2013-01-27 | 1 | -0/+12 |
| | | | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173629 | ||||
| * | [XCore] Add missing 1r instructions. | Richard Osborne | 2013-01-27 | 1 | -0/+27 |
| | | | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173624 | ||||
| * | [XCore] Add missing 0r instructions. | Richard Osborne | 2013-01-27 | 1 | -0/+51 |
| | | | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173623 | ||||
| * | Add instruction encodings / disassembly support for l4r instructions. | Richard Osborne | 2013-01-25 | 1 | -0/+11 |
| | | | | | llvm-svn: 173501 | ||||
| * | Add instruction encodings / disassembly support for l5r instructions. | Richard Osborne | 2013-01-25 | 1 | -0/+11 |
| | | | | | llvm-svn: 173479 | ||||
| * | Add instruction encodings / disassembly support for l6r instructions. | Richard Osborne | 2013-01-23 | 1 | -0/+5 |
| | | | | | llvm-svn: 173288 | ||||
| * | Add instruction encodings / disassembly support for u10 / lu10 instructions. | Richard Osborne | 2013-01-22 | 1 | -0/+14 |
| | | | | | llvm-svn: 173204 | ||||
| * | Add instruction encodings / disassembly support for u6 / lu6 instructions. | Richard Osborne | 2013-01-21 | 1 | -0/+50 |
| | | | | | llvm-svn: 173086 | ||||
| * | Add instruction encoding / disassembly support for ru6 / lru6 instructions. | Richard Osborne | 2013-01-21 | 1 | -0/+80 |
| | | | | | llvm-svn: 173085 | ||||
| * | Add instruction encodings / disassembly support for l2rus instructions. | Richard Osborne | 2013-01-20 | 1 | -0/+11 |
| | | | | | llvm-svn: 172987 | ||||
| * | Add instruction encodings / disassembly support for l3r instructions. | Richard Osborne | 2013-01-20 | 1 | -0/+44 |
| | | | | | llvm-svn: 172986 | ||||
| * | Add instruction encodings / disassembler support for 2rus instructions. | Richard Osborne | 2013-01-20 | 1 | -0/+23 |
| | | | | | llvm-svn: 172985 | ||||
| * | Add instruction encodings / disassembly support 3r instructions. | Richard Osborne | 2013-01-20 | 1 | -0/+38 |
| | | | | | | | | | It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. llvm-svn: 172984 | ||||
| * | Add instruction encodings / disassembly support for l2r instructions. | Richard Osborne | 2012-12-17 | 1 | -0/+32 |
| | | | | | llvm-svn: 170345 | ||||
| * | Add instruction encodings for PEEK and ENDIN. | Richard Osborne | 2012-12-17 | 1 | -0/+6 |
| | | | | | | | Previously these were marked with the wrong format. llvm-svn: 170334 | ||||
| * | Add instruction encodings / disassembly support for rus instructions. | Richard Osborne | 2012-12-17 | 1 | -0/+20 |
| | | | | | llvm-svn: 170330 | ||||
| * | Add instruction encodings for ZEXT and SEXT. | Richard Osborne | 2012-12-17 | 1 | -0/+6 |
| | | | | | | | Previously these were marked with the wrong format. llvm-svn: 170327 | ||||
| * | Add instruction encodings / disassembly support for 2r instructions. | Richard Osborne | 2012-12-17 | 1 | -0/+74 |
| | | | | | llvm-svn: 170323 | ||||
| * | Add instruction encodings / disassembly support for 0r instructions. | Richard Osborne | 2012-12-17 | 1 | -0/+20 |
| | | | | | llvm-svn: 170322 | ||||
| * | Add tests for disassembly of 1r XCore instructions. | Richard Osborne | 2012-12-16 | 2 | -0/+45 |
| llvm-svn: 170295 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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