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* [ARM] Add support for unpredictable MVN instructions.Yvan Roux2018-02-011-0/+38
| | | | | | | | | | | | | | | This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
* [ARM] Armv8-R DFB instructionSam Parker2017-12-212-0/+12
| | | | | | | | Implement MC support for the Armv8-R 'Data Full Barrier' instruction. Differential Revision: https://reviews.llvm.org/D41430 llvm-svn: 321256
* [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM modeAndre Vieira2017-10-182-0/+85
| | | | | | Differential Revision: https://reviews.llvm.org/D38347 llvm-svn: 316085
* [ARM] v8.3-a complex number supportSam Parker2017-09-292-0/+132
| | | | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 llvm-svn: 314511
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-09-222-0/+183
| | | | | | | Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 313979
* [ARM][AArch64] v8.3-A Javascript ConversionSam Parker2017-08-222-0/+20
| | | | | | | | | | Armv8.3-A adds instructions that convert a double-precision floating point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance. Differential Revision: https://reviews.llvm.org/D36785 llvm-svn: 311448
* [ARM] Assembler support for the ARMv8.2a dot product instructionsSjoerd Meijer2017-08-112-0/+62
| | | | | | | | | Commit r310480 added the AArch64 ARMv8.2a dot product instructions; this adds the AArch32 instructions. Differential Revision: https://reviews.llvm.org/D36575 llvm-svn: 310701
* Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR"Tim Northover2017-08-083-183/+8
| | | | | | | | This reverts r310243. Only MVFR2 is actually restricted to v8 and it'll be a little while before we can get a proper fix together. Better that we allow incorrect code than reject correct in the meantime. llvm-svn: 310384
* [ARM] Fix assembly and disassembly for VMRS/VMSRAndre Vieira2017-08-073-8/+183
| | | | | | | | | | | | | | | | This patch addresses two issues with assembly and disassembly for VMRS/VMSR: 1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are accepted for non ARMv8-A targets. 2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC. This patch addresses those issues and adds tests for these cases. Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 310243
* [ARM] Saturation instructions are DSP-onlyRenato Golin2016-07-251-1/+1
| | | | | | | | | | | The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-032-0/+12
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* [LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC.Mandeep Singh Grang2016-04-191-1/+1
| | | | | | | | | | | | Summary: Removed unwanted --check-prefix=CHECK from numerous unit tests. Reviewers: t.p.northover, dblaikie, uweigand, MatzeB, tstellarAMD, mcrosier Subscribers: mcrosier, dsanders Differential Revision: http://reviews.llvm.org/D19279 llvm-svn: 266834
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-251-0/+25
| | | | | | | | This patch was originally committed as r257884, but was reverted due to windows failures. The cause of these failures has been fixed under r258677, hence re-committing the original patch. llvm-svn: 258682
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-254-0/+746
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
* # This is a combination of 2 commits.Reid Kleckner2016-01-151-25/+0
| | | | | | | | | | | | | | | | # The first commit's message is: Revert "[ARM] Add DSP build attribute and extension targeting" This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc. # This is the 2nd commit message: Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline" This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5. llvm-svn: 257916
* [ARM] Add new system registers to ARMv8-M Baseline/MainlineBradley Smith2016-01-151-0/+25
| | | | llvm-svn: 257884
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-164-746/+0
| | | | | | This reverts commit r255762. llvm-svn: 255806
* [ARM] Add ARMv8.2-A FP16 vector instructionsOliver Stannard2015-12-164-0/+1166
| | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. Differential Revision: http://reviews.llvm.org/D15039 llvm-svn: 255764
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-164-0/+746
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 255762
* [ARM] Allow SP in rGPR, starting from ARMv8Artyom Skrobov2015-10-282-6/+27
| | | | | | | | | | | | | | | | | Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
* [ARM] Add v8.1a "Privileged Access Never" extensionVladimir Sukharev2015-04-162-0/+28
| | | | | | | | | | Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8504 llvm-svn: 235087
* [ARM] Fix some non-portable shell syntax in r233301's testsJustin Bogner2015-03-261-2/+2
| | | | | | | | | | The "|&" operator isn't POSIX, so it can fail depending on the host's default shell. Avoid it. There were also a couple of places that did "2>1", but this creates a file called "1". They clearly meant "2>&1". llvm-svn: 233309
* [ARM] Add v8.1a "Rounding Double Multiply Add/Subtract" extensionVladimir Sukharev2015-03-264-0/+289
| | | | | | | | | | Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8503 llvm-svn: 233301
* Add a bunch of CHECK missing colons in tests. NFC.Ahmed Bougacha2015-03-141-3/+3
| | | | | | Some wouldn't pass; fixed most, the rest will be fixed separately. llvm-svn: 232239
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-022-3/+109
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* Add post-decode checking of HVC instruction.Charlie Turner2014-12-011-0/+10
| | | | | | | | | | | | Add checkDecodedInstruction for post-decode checking of instructions, to catch the corner cases like HVC that don't fit into the general pattern. Needed to check for an invalid condition field in instruction encoding despite HVC not taking a predicate. Patch by Matthew Wahab. Change-Id: I48e28de981d7a9e43569594da3c45fb478b4f795 llvm-svn: 222992
* Add Thumb HVC and ERET virtualisation extension instructions.Charlie Turner2014-12-011-0/+61
| | | | | | | Patch by Matthew Wahab. Change-Id: I131f71c1150d5fa797066a18e09d526c19bf9016 llvm-svn: 222990
* Add ARM ERET and HVC virtualisation extension instructions.Charlie Turner2014-12-011-0/+41
| | | | | | | Patch by Matthew Wahab. Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb llvm-svn: 222989
* Fix wrong encoding of MRSBanked.Charlie Turner2014-11-281-33/+33
| | | | | | | Patch by Matthew Wahab. Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc llvm-svn: 222920
* Fix bashism in tests added by r221341Oliver Stannard2014-11-051-2/+2
| | | | llvm-svn: 221342
* [ARM] Honor FeatureD16 in the assembler and disassemblerOliver Stannard2014-11-051-0/+23
| | | | | | | | | | | | | | | Some ARM FPUs only have 16 double-precision registers, rather than the normal 32. LLVM represents this with the D16 target feature. This is currently used by CodeGen to avoid using high registers when they are not available, but the assembler and disassembler do not. I fix this in the assmebler and disassembler rather than the InstrInfo.td files, as the latter would require a large number of changes everywhere one of the floating-point instructions is referenced in the backend. This solution is similar to the one used for co-processor numbers and MSR masks. llvm-svn: 221341
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-032-2/+2
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* [Thumb2] Improve disassembly of memory hintsOliver Stannard2014-10-231-0/+69
| | | | | | | | | Currently, the ARM disassembler will disassemble the Thumb2 memory hint instructions (PLD, PLDW and PLI), even for targets which do not have these instructions. This patch adds the required checks to the disassmebler. llvm-svn: 220472
* Thumb2 M-class MSR instruction support changesRenato Golin2014-09-012-13/+14
| | | | | | | | | | | | This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. llvm-svn: 216874
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-152-0/+303
| | | | | | | | | | These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
* Allow only disassembling of M-class MSR masks that the assembler knows how ↵James Molloy2014-08-012-4/+125
| | | | | | | | | | to assemble back. Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
* ARM: honor hex immediate formatting for ldr/str i12 offsets.Jim Grosbach2014-06-111-0/+6
| | | | | | | | | | | | | | | | | Previously we would always print the offset as decimal, regardless of the formatting requested. Now we use the formatImm() helper so the value is printed as the client (LLDB in the motivating example) requested. Before: ldr.w r8, [sp, #180] @ always After: ldr.w r8, [sp, #0xb4] @ when printing hex immediates ldr.w r8, [sp, #0180] @ when printing decimal immediates rdar://17237103 llvm-svn: 210701
* llvm-mc: Add option for prefering hex format disassembly.Jim Grosbach2014-06-111-1/+1
| | | | | | | | | Previously there was a separate mode entirely (--hdis vs. --disassemble). It makes a bit more sense for the immediate printing style to be a flag for --disassmeble rather than an entirely different thing. llvm-svn: 210700
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-141-39/+0
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructionsSaleem Abdulrasool2014-01-121-4/+4
| | | | | | | | | | | | | The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. llvm-svn: 199032
* ARM: fix regression caused by r198914Saleem Abdulrasool2014-01-101-0/+12
| | | | | | | | The disassembler would no longer be able to disambiguage between the two variants (explicit immediate #0 vs implicit, omitted #0) for the ldrt, strt, ldrbt, strbt mnemonics as both versions indicated the disassembler routine. llvm-svn: 198944
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-112-0/+11
| | | | llvm-svn: 194416
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-082-0/+202
| | | | | | ARMv8 (Thumb encodings) llvm-svn: 194263
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+167
| | | | | | ARMv8 (ARM encodings) llvm-svn: 194262
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+35
| | | | | | ARMv8 (ARM encodings) llvm-svn: 194261
* [ARM] NEON instructions were erroneously decoded from certain invalid encodingsArtyom Skrobov2013-10-301-0/+8
| | | | llvm-svn: 193705
* Make ARM hint ranges consistent, and add tests for these rangesArtyom Skrobov2013-10-231-2/+6
| | | | llvm-svn: 193238
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-221-0/+16
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-182-13/+8
| | | | | | Patch by Artyom Skrobov llvm-svn: 192972
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