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| author | Charlie Turner <charlie.turner@arm.com> | 2014-11-28 15:01:06 +0000 |
|---|---|---|
| committer | Charlie Turner <charlie.turner@arm.com> | 2014-11-28 15:01:06 +0000 |
| commit | db6c5e7afac73324ae9b2139f3ab6bc4b228b2c7 (patch) | |
| tree | 87442365457344715d24b3e4828206676abf7018 /llvm/test/MC/Disassembler/ARM | |
| parent | 30bd345613725e0bd875c88ae4ea57908154e10b (diff) | |
| download | bcm5719-llvm-db6c5e7afac73324ae9b2139f3ab6bc4b228b2c7.tar.gz bcm5719-llvm-db6c5e7afac73324ae9b2139f3ab6bc4b228b2c7.zip | |
Fix wrong encoding of MRSBanked.
Patch by Matthew Wahab.
Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc
llvm-svn: 222920
Diffstat (limited to 'llvm/test/MC/Disassembler/ARM')
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/move-banked-regs-arm.txt | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/llvm/test/MC/Disassembler/ARM/move-banked-regs-arm.txt b/llvm/test/MC/Disassembler/ARM/move-banked-regs-arm.txt index dd1d463f242..b92c5779a66 100644 --- a/llvm/test/MC/Disassembler/ARM/move-banked-regs-arm.txt +++ b/llvm/test/MC/Disassembler/ARM/move-banked-regs-arm.txt @@ -1,13 +1,13 @@ @ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s -[0x00,0x22,0x20,0xe1] -[0x00,0x32,0x21,0xe1] -[0x00,0x52,0x22,0xe1] -[0x00,0x72,0x23,0xe1] -[0x00,0xb2,0x24,0xe1] -[0x00,0x12,0x25,0xe1] -[0x00,0x22,0x26,0xe1] +[0x00,0x22,0x00,0xe1] +[0x00,0x32,0x01,0xe1] +[0x00,0x52,0x02,0xe1] +[0x00,0x72,0x03,0xe1] +[0x00,0xb2,0x04,0xe1] +[0x00,0x12,0x05,0xe1] +[0x00,0x22,0x06,0xe1] @ CHECK: mrs r2, r8_usr @ CHECK: mrs r3, r9_usr @ CHECK: mrs r5, r10_usr @@ -16,14 +16,14 @@ @ CHECK: mrs r1, sp_usr @ CHECK: mrs r2, lr_usr -[0x00,0x22,0x28,0xe1] -[0x00,0x32,0x29,0xe1] -[0x00,0x52,0x2a,0xe1] -[0x00,0x72,0x2b,0xe1] -[0x00,0xb2,0x2c,0xe1] -[0x00,0x12,0x2d,0xe1] -[0x00,0x22,0x2e,0xe1] -[0x00,0x32,0x6e,0xe1] +[0x00,0x22,0x08,0xe1] +[0x00,0x32,0x09,0xe1] +[0x00,0x52,0x0a,0xe1] +[0x00,0x72,0x0b,0xe1] +[0x00,0xb2,0x0c,0xe1] +[0x00,0x12,0x0d,0xe1] +[0x00,0x22,0x0e,0xe1] +[0x00,0x32,0x4e,0xe1] @ CHECK: mrs r2, r8_fiq @ CHECK: mrs r3, r9_fiq @ CHECK: mrs r5, r10_fiq @@ -33,44 +33,44 @@ @ CHECK: mrs r2, lr_fiq @ CHECK: mrs r3, SPSR_fiq -[0x00,0x43,0x20,0xe1] -[0x00,0x93,0x21,0xe1] -[0x00,0x13,0x60,0xe1] +[0x00,0x43,0x00,0xe1] +[0x00,0x93,0x01,0xe1] +[0x00,0x13,0x40,0xe1] @ CHECK: mrs r4, lr_irq @ CHECK: mrs r9, sp_irq @ CHECK: mrs r1, SPSR_irq -[0x00,0x13,0x22,0xe1] -[0x00,0x33,0x23,0xe1] -[0x00,0x53,0x62,0xe1] +[0x00,0x13,0x02,0xe1] +[0x00,0x33,0x03,0xe1] +[0x00,0x53,0x42,0xe1] @ CHECK: mrs r1, lr_svc @ CHECK: mrs r3, sp_svc @ CHECK: mrs r5, SPSR_svc -[0x00,0x53,0x24,0xe1] -[0x00,0x73,0x25,0xe1] -[0x00,0x93,0x64,0xe1] +[0x00,0x53,0x04,0xe1] +[0x00,0x73,0x05,0xe1] +[0x00,0x93,0x44,0xe1] @ CHECK: mrs r5, lr_abt @ CHECK: mrs r7, sp_abt @ CHECK: mrs r9, SPSR_abt -[0x00,0x93,0x26,0xe1] -[0x00,0xb3,0x27,0xe1] -[0x00,0xc3,0x66,0xe1] +[0x00,0x93,0x06,0xe1] +[0x00,0xb3,0x07,0xe1] +[0x00,0xc3,0x46,0xe1] @ CHECK: mrs r9, lr_und @ CHECK: mrs r11, sp_und @ CHECK: mrs r12, SPSR_und -[0x00,0x23,0x2c,0xe1] -[0x00,0x43,0x2d,0xe1] -[0x00,0x63,0x6c,0xe1] +[0x00,0x23,0x0c,0xe1] +[0x00,0x43,0x0d,0xe1] +[0x00,0x63,0x4c,0xe1] @ CHECK: mrs r2, lr_mon @ CHECK: mrs r4, sp_mon @ CHECK: mrs r6, SPSR_mon -[0x00,0x63,0x2e,0xe1] -[0x00,0x83,0x2f,0xe1] -[0x00,0xa3,0x6e,0xe1] +[0x00,0x63,0x0e,0xe1] +[0x00,0x83,0x0f,0xe1] +[0x00,0xa3,0x4e,0xe1] @ CHECK: mrs r6, elr_hyp @ CHECK: mrs r8, sp_hyp @ CHECK: mrs r10, SPSR_hyp |
