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| author | Charlie Turner <charlie.turner@arm.com> | 2014-12-01 08:50:27 +0000 |
|---|---|---|
| committer | Charlie Turner <charlie.turner@arm.com> | 2014-12-01 08:50:27 +0000 |
| commit | 30895f9ab8cd9ce82f695147dc517fd44b8a21dd (patch) | |
| tree | 61f452e301245b8dd5002e3bee9f892c523f241f /llvm/test/MC/Disassembler/ARM | |
| parent | 3ae427d81183d6f7675811ed7d6ffa365adc1938 (diff) | |
| download | bcm5719-llvm-30895f9ab8cd9ce82f695147dc517fd44b8a21dd.tar.gz bcm5719-llvm-30895f9ab8cd9ce82f695147dc517fd44b8a21dd.zip | |
Add post-decode checking of HVC instruction.
Add checkDecodedInstruction for post-decode checking of instructions, to catch
the corner cases like HVC that don't fit into the general pattern. Needed to
check for an invalid condition field in instruction encoding despite HVC not
taking a predicate.
Patch by Matthew Wahab.
Change-Id: I48e28de981d7a9e43569594da3c45fb478b4f795
llvm-svn: 222992
Diffstat (limited to 'llvm/test/MC/Disassembler/ARM')
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt new file mode 100644 index 00000000000..1daada98d67 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -disassemble -triple armv7a -mcpu=cortex-a15 %s 2>&1 | FileCheck --check-prefix=CHECK-ARM %s + +# HVC (ARM) +[0x7f,0xff,0x4f,0xf1] +# CHECK-ARM: warning: invalid instruction encoding + +[0x70,0xff,0x4f,0x01] +[0x7f,0xff,0x4f,0xd1] +# CHECK-ARM: warning: potentially undefined instruction encoding +# CHECK-ARM: warning: potentially undefined instruction encoding |
