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* [ARM] Make coprocessor number restrictions consistent.Simon Tatham2019-06-271-12/+12
| | | | | | | | | | | | | | | | | | | | | | Different versions of the Arm architecture disallow the use of generic coprocessor instructions like MCR and CDP on different sets of coprocessors. This commit centralises the check of the coprocessor number so that it's consistent between assembly and disassembly, and also updates it for the new restrictions in Arm v8.1-M. New tests added that check all the coprocessor numbers; old tests updated, where they used a number that's now become illegal in the context in question. Reviewers: DavidSpickett, ostannard Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63863 llvm-svn: 364532
* [ARM] Add missing Thumb2 assembler diagnostics.Eli Friedman2018-06-281-1/+51
| | | | | | | | | | Mostly just adding checks for Thumb2 instructions which correspond to ARM instructions which already had diagnostics. While I'm here, also fix ARM-mode strd to check the input registers correctly. Differential Revision: https://reviews.llvm.org/D48610 llvm-svn: 335909
* [ARM] Add support for unpredictable MVN instructions.Yvan Roux2018-02-011-0/+7
| | | | | | | | | | | | | | | This fixes bugzilla 33011 https://bugs.llvm.org/show_bug.cgi?id=33011 Defines bits {19-16} as zero or unpredictable as specified by the ARM ARM in sections A8.8.116 and A8.8.117. It fixes also the usage of PC register as destination register for MVN register-shifted register version as specified in A8.8.117. Differential Revision: https://reviews.llvm.org/D41905 llvm-svn: 323954
* Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard2017-12-041-3/+3
| | | | | | | | This is causing a failure in the llvm-clang-x86_64-expensive-checks-win buildbot, and I can't reproduce it locally, so reverting until I can work out what is wrong. llvm-svn: 319654
* [Asm, ARM] Add fallback diag for multiple invalid operandsOliver Stannard2017-12-041-3/+3
| | | | | | | | | | | | | | | | This adds a "invalid operands for instruction" diagnostic for instructions where there is an instruction encoding with the correct mnemonic and which is available for this target, but where multiple operands do not match those which were provided. This makes it clear that there is some combination of operands that is valid for the current target, which the default diagnostic of "invalid instruction" does not. Since this is a very general error, we only emit it if we don't have a more specific error. Differential revision: https://reviews.llvm.org/D36747 llvm-svn: 319649
* [Asm] Improve "too few operands" errorsOliver Stannard2017-11-211-0/+6
| | | | | | | | | | - We can still emit this error if the actual instruction has two or more operands missing compared to the expected one. - We should only emit this error once per instruction. Differential revision: https://reviews.llvm.org/D36746 llvm-svn: 318770
* [ARM] Error for invalid shift in memory operandOliver Stannard2017-10-241-0/+3
| | | | | | | | | | Report a diagnostic when we fail to parse a shift in a memory operand because the shift type is not an identifier. Without this, we were silently ignoring the whole instruction. Differential revision: https://reviews.llvm.org/D39237 llvm-svn: 316441
* [ARM, Asm] Add diagnostics for general-purpose register operandsOliver Stannard2017-10-101-6/+10
| | | | | | | | | | | | | | | This adds diagnostic strings for the ARM general-purpose register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, rGPR, requires C++ code to select the correct error message, as that class contains different registers in pre-v8 and v8 targets. The rest can all have their diagnostic strings stored in the tablegen description of them. Differential revision: https://reviews.llvm.org/D36692 llvm-svn: 315303
* [ARM] Add diag string for movw/movt immediates in assemblyOliver Stannard2017-10-041-2/+2
| | | | | | | | | This adds diagnostics for invalid immediate operands to the MOVW and MOVT instructions (ARM and Thumb). Differential revision: https://reviews.llvm.org/D31879 llvm-svn: 314888
* [ARM, Asm] Change grammar of immediate operand diagnosticsOliver Stannard2017-10-041-28/+28
| | | | | | | | | | | | | | | | | Currently, our diagnostics for assembly operands are not consistent. Some start with (for example) "immediate operand must be ...", and some with "operand must be an immediate ...". I think the latter form is preferable for a few reasons: * It's unambiguous that it is referring to the expected type of operand, not the type the user provided. For example, the user could provide an register operand, and get a message taking about an operand is if it is already an immediate, just not in the accepted range. * It allows us to have a consistent style once we add diagnostics for operands that could take two forms, for example a label or pc-relative memory operand. Differential revision: https://reviews.llvm.org/D36689 llvm-svn: 314887
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-031-26/+36
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* ARMAsmParser: clean up of isImmediate functionsSjoerd Meijer2017-04-031-24/+35
| | | | | | | | | | | | | | | | | - we are now using immediate AsmOperands so that the range check functions are tablegen'ed. - Big bonus is that error messages become much more accurate, i.e. instead of a useless "invalid operand" error message it will not say that the immediate operand must in range [x,y], which is why regression tests needed updating. More tablegen operand descriptions could probably benefit from using immediateAsmOperand, but this is a first good step to get rid of most of the nearly identical range check functions. I will address the remaining immediate operands in next clean ups. Differential Revision: https://reviews.llvm.org/D31333 llvm-svn: 299358
* [ARM] Diagnose ARM MOVT without :lower16: or :upper16: expressionOliver Stannard2017-03-141-0/+3
| | | | | | | | | | | This instruction was missing from the list of opcodes that we check, so we were hitting an llvm_unreachable in ARMMCCodeEmitter.cpp for the ARM MOVT instruction, rather than the diagnostic that is emitted for the other MOVW/MOVT instructions. Differential revision: https://reviews.llvm.org/D30936 llvm-svn: 297739
* [ARM] Allow SP in rGPR, starting from ARMv8Artyom Skrobov2015-10-281-30/+34
| | | | | | | | | | | | | | | | | Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-021-0/+80
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-0/+32
| | | | | | | | LDRB/LDRSB instructions. The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214500
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-0/+32
| | | | | | | | LDRH/LDRSH instructions. The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214499
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR ↵Tilmann Scheller2014-08-011-0/+17
| | | | | | | | instructions. The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. llvm-svn: 214498
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH ↵Tilmann Scheller2014-07-241-0/+16
| | | | | | | | instructions. The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior. llvm-svn: 213850
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB ↵Tilmann Scheller2014-07-231-0/+16
| | | | | | | | instructions. The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior. llvm-svn: 213750
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR ↵Tilmann Scheller2014-07-231-0/+17
| | | | | | | | instructions. The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior. llvm-svn: 213745
* ARM: mark UBFX as not allowing PC.Tim Northover2014-06-231-0/+18
| | | | | | | | | Strictly, it's unpredictable. But we don't quite model that yet and an error is better than ignoring the issue. This one somehow got left out before though. rdar://problem/15997748 llvm-svn: 211490
* Change the ARM assembler to require a :lower16: or :upper16 on non-constantKevin Enderby2014-04-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | expressions for mov instructions instead of silently truncating by default. For the ARM assembler, we want to avoid misleadingly allowing something like "mov r0, <symbol>" especially when we turn it into a movw and the expression <symbol> does not have a :lower16: or :upper16" as part of the expression. We don't want the behavior of silently truncating, which can be unexpected and lead to bugs that are difficult to find since this is an easy mistake to make. This does change the previous behavior of llvm but actually matches an older gnu assembler that would not allow this but print less useful errors of like “invalid constant (0x927c0) after fixup” and “unsupported relocation on symbol foo”. The error for llvm is "immediate expression for mov requires :lower16: or :upper16" with correct location information on the operand as shown in the added test cases. rdar://12342160 llvm-svn: 206669
* ARM: diagnose invalid system LDM/STMTim Northover2013-11-121-0/+5
| | | | | | | | | | | | | The system LDM and STM instructions can't usually writeback to the base register. The one exception is when an LDM is actually an exception-return (i.e. contains PC in the register list). (There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there is no positive test). rdar://problem/15223374 llvm-svn: 194512
* [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 ↵Artyom Skrobov2013-11-081-0/+5
| | | | | | as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings llvm-svn: 194253
* ARM: mark various aliases with their architecture requirements.Tim Northover2013-10-241-0/+17
| | | | | | | | | | If an alias inherits directly from InstAlias then it doesn't get any default "Requires" values, so llvm-mc will allow it even on architectures that don't support the underlying instruction. This tidies up the obvious VFP and NEON cases I found. llvm-svn: 193340
* ARM: fix assert on unpredictable POP instruction.Tim Northover2013-10-241-3/+5
| | | | | | | | | | | POP instructions are aliased to the ARM LDM variants but have different syntax. This caused two problems: we tried to access a non-existent operand to annotate the '!', and the error message didn't make much sense. With some vigorous hand-waving in the error message both problems can be fixed. llvm-svn: 193322
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-221-0/+7
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-051-0/+22
| | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. llvm-svn: 190053
* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-261-0/+14
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
* ARM: allow predicated barriers in Thumb modeTim Northover2013-06-261-0/+14
| | | | | | | The barrier instructions are only "always-execute" in ARM mode, they can quite happily sit inside an IT block in Thumb. llvm-svn: 184964
* Change the arm assembler to support this from the v7c spec:Kevin Enderby2013-06-181-0/+3
| | | | | | | | | | | | | | | "When assembling to the ARM instruction set, the .N qualifier produces an assembler error and the .W qualifier has no effect." In the pre-matcher handler in the asm parser the ".w" (wide) qualifier when in ARM mode is now discarded. And an error message is now produced when the ".n" (narrow) qualifier is used in ARM mode. Test cases for these were added. rdar://14064574 llvm-svn: 184224
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+5
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* Test case for r165480.Craig Topper2012-10-101-0/+10
| | | | llvm-svn: 165594
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-221-0/+40
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
* ARM: Add a better diagnostic for some out of range immediates.Jim Grosbach2012-06-221-6/+6
| | | | | | | | | | | As an example of how the custom DiagnosticType can be used to provide better operand-mismatch diagnostics, add a custom diagnostic for the imm0_15 operand class used for several system instructions. Update the tests to expect the improved diagnostic. rdar://8987109 llvm-svn: 159051
* Replace assertion failure for badly formatted CPS instrution with error message.Richard Barton2012-06-141-0/+6
| | | | llvm-svn: 158445
* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-1/+1
| | | | | | | | | | It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 llvm-svn: 152943
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+10
| | | | llvm-svn: 141786
* Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.Jim Grosbach2011-09-191-2/+2
| | | | llvm-svn: 140047
* ARM fix assembly parser handling of ranges in register lists.Jim Grosbach2011-09-141-1/+9
| | | | | | | | | Clean up register list handling in general a bit to explicitly check things like all the registers being from the same register class. rdar://8883573 llvm-svn: 139707
* ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-101-0/+14
| | | | llvm-svn: 137244
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-0/+11
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* ARM assembly parsing and encoding for extend instructions.Jim Grosbach2011-07-271-0/+34
| | | | | | | Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
* ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach2011-07-261-0/+12
| | | | llvm-svn: 136110
* ARM parsing and encoding for SVC instruction.Jim Grosbach2011-07-261-0/+7
| | | | llvm-svn: 136090
* Update ARM STM tests. Fix check: prefix for diagnostic tests.Jim Grosbach2011-07-261-60/+68
| | | | llvm-svn: 136088
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-251-0/+11
| | | | llvm-svn: 136006
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-251-0/+40
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach2011-07-221-0/+16
| | | | | | | Add parsing and diagnostics for malformed inputs. Tests for diagnostics and for correct encodings. llvm-svn: 135776
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