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* GlobalISel: Handle some odd splits in fewerElementsVectorMatt Arsenault2019-01-301-3/+75
| | | | | | Also add some quick hacks to AMDGPU legality for the tests. llvm-svn: 352591
* GlobalISel: Handle more cases for widenScalar for G_STOREMatt Arsenault2019-01-301-0/+99
| | | | llvm-svn: 352585
* [PowerPC] more opportunity for converting reg+reg to reg+immChen Zheng2019-01-301-0/+17
| | | | | | Differential Revision: https://reviews.llvm.org/D57314 llvm-svn: 352583
* GlobalISel: Verify memory size for load/storeMatt Arsenault2019-01-306-148/+210
| | | | llvm-svn: 352578
* [WebAssembly] Lower SCALAR_TO_VECTOR to splatsThomas Lively2019-01-291-0/+43
| | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57269 llvm-svn: 352568
* GlobalISel: Verify pointer castsMatt Arsenault2019-01-293-14/+13
| | | | | | | Not sure if the old AArch64 tests should be just deleted or not. llvm-svn: 352562
* GlobalISel: Partially implement widenScalar for MERGE_VALUESMatt Arsenault2019-01-292-24/+184
| | | | llvm-svn: 352560
* [AArch64][GlobalISel] Unmerge into scalars from a vector should use FPR bank.Amara Emerson2019-01-291-0/+26
| | | | | | | | | This currently shows up as a selection fallback since the dest regs were given GPR banks but the source was a vector FPR reg. Differential Revision: https://reviews.llvm.org/D57408 llvm-svn: 352545
* [DAGCombiner] fold extract_subvector of extract_subvectorSanjay Patel2019-01-2918-400/+404
| | | | | | | | | | | | | | | This is the sibling fold for insert-of-insert that was added with D56604. Now that we have x86 shuffle narrowing (D57156), this change shows improvements for lots of AVX512 reduction code (not sure that we would ever expect extract-of-extract otherwise). There's a small regression in some of the partial-permute tests (extracting followed by splat). That is tracked by PR40500: https://bugs.llvm.org/show_bug.cgi?id=40500 Differential Revision: https://reviews.llvm.org/D57336 llvm-svn: 352528
* GlobalISel: Fix narrowScalar for load/store with different mem sizeMatt Arsenault2019-01-292-0/+132
| | | | | | | | | | This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
* [x86] add tests for vector bool math; NFCSanjay Patel2019-01-291-0/+25
| | | | llvm-svn: 352520
* [AArch64] add tests for vector bool math; NFCSanjay Patel2019-01-291-0/+29
| | | | llvm-svn: 352519
* [X86][Btver2] Improved latency/throughput model for scalar int-to-float ↵Andrea Di Biagio2019-01-292-16/+16
| | | | | | | | | | | | | | conversions. Account for bypass delays when computing the latency of scalar int-to-float conversions. On Jaguar we need to account for an extra 6cy latency (see AMD fam16h SOG). This patch also fixes the number of micropcodes for the register-memory variants of scalar int-to-float conversions. Differential Revision: https://reviews.llvm.org/D57148 llvm-svn: 352518
* Adjust documentation for git migration.James Y Knight2019-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes most references to the paths: llvm.org/svn/ llvm.org/git/ llvm.org/viewvc/ github.com/llvm-mirror/ github.com/llvm-project/ reviews.llvm.org/diffusion/ to instead point to https://github.com/llvm/llvm-project. This is *not* a trivial substitution, because additionally, all the checkout instructions had to be migrated to instruct users on how to use the monorepo layout, setting LLVM_ENABLE_PROJECTS instead of checking out various projects into various subdirectories. I've attempted to not change any scripts here, only documentation. The scripts will have to be addressed separately. Additionally, I've deleted one document which appeared to be outdated and unneeded: lldb/docs/building-with-debug-llvm.txt Differential Revision: https://reviews.llvm.org/D57330 llvm-svn: 352514
* Reversing the checkin for version 352484 as tests are failing.Ayonam Ray2019-01-293-165/+39
| | | | llvm-svn: 352504
* [AMDGPU] Fix a weird WWM intrinsic issue.Neil Henning2019-01-291-0/+47
| | | | | | | | | | | I found a really strange WWM issue through a very convoluted shader that essentially boils down to a bug in SIInstrInfo where canReadVGPR did not correctly identify that WWM is like a copy and can have a VGPR as its source. Differential Revision: https://reviews.llvm.org/D56002 llvm-svn: 352500
* [CodeGen] Omit range checks from jump tables when lowering switches with ↵Ayonam Ray2019-01-293-39/+165
| | | | | | | | | | | | | | | | | unreachable default During the lowering of a switch that would result in the generation of a jump table, a range check is performed before indexing into the jump table, for the switch value being outside the jump table range and a conditional branch is inserted to jump to the default block. In case the default block is unreachable, this conditional jump can be omitted. This patch implements omitting this conditional branch for unreachable defaults. Review ID: D52002 Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev llvm-svn: 352484
* [X86] Add PR40483 test caseSimon Pilgrim2019-01-291-0/+57
| | | | llvm-svn: 352480
* [WebAssembly] Re-enable main-function signature rewritingDan Gohman2019-01-297-20/+35
| | | | | | | | | | | | | | | | Re-enable the code to rewrite main-function signatures into "int main(int argc, char *argv[])", but limited to only handling the case of "int main(void)", so that it doesn't silently strip an argument in the "int main(int argc, char *argv[], char *envp[])" case. This allows main to be called by C startup code, since WebAssembly requires caller and callee signatures to match, so it can't rely on passing main a different number of arguments than it expects. Differential Revision: https://reviews.llvm.org/D57323 llvm-svn: 352479
* [X86] Fix linux32 pic tests to use correct relocation model (PR39684)Simon Pilgrim2019-01-291-331/+1246
| | | | | | Differential Revision: https://reviews.llvm.org/D57301 llvm-svn: 352476
* [ARM] Use sub for negative offset load/store in thumb1David Green2019-01-291-36/+24
| | | | | | | | | | | This attempts to optimise negative values used in load/store operands a little. We currently try to selct them as rr, materialising the negative constant using a MOV/MVN pair. This instead selects ri with an immediate of 0, forcing the add node to become a simpler sub. Differential Revision: https://reviews.llvm.org/D57121 llvm-svn: 352475
* [X86] Regenerate abi-isel.ll testSimon Pilgrim2019-01-291-5/+6
| | | | | | Adds note requested in D57301 and fixes some missing GOTPCREL addressmath checks llvm-svn: 352474
* [ARM] Add extra testcases for D57121. NFCDavid Green2019-01-291-0/+482
| | | | llvm-svn: 352472
* [COFF, ARM64] Don't put jump table into a separate COFF section for ↵Martin Storsjo2019-01-291-0/+48
| | | | | | | | | | | | | | | | | | | | | | EK_LabelDifference32 Windows ARM64 has PIC relocation model and uses jump table kind EK_LabelDifference32. This produces jump table entry as ".word LBB123 - LJTI1_2" which represents the distance between the block and jump table. A new relocation type (IMAGE_REL_ARM64_REL32) is needed to do the fixup correctly if they are in different COFF section. This change saves the jump table to the same COFF section as the associated code. An ideal fix could be utilizing IMAGE_REL_ARM64_REL32 relocation type. Patch by Tom Tan! Differential Revision: https://reviews.llvm.org/D57277 llvm-svn: 352465
* [CodeGenPrepare] Handle all debug calls in dupRetToEnableTailCallOpts()Jonas Paulsson2019-01-291-0/+171
| | | | | | | | | | | | This patch makes sure that a debug value that is after the bitcast in dupRetToEnableTailCallOpts() is also skipped. The reduced test case is from SPEC-2006 on SystemZ. Review: Vedant Kumar, Wolfgang Pieb https://reviews.llvm.org/D57050 llvm-svn: 352462
* [WebAssembly] Handle more types of uses in WebAssemblyAddMissingPrototypesSam Clegg2019-01-291-4/+25
| | | | | | | | | | | | | | Previously we were only handling bitcast operations, however prototypeless functions can also appear in other places such as comparisons and as function params. Switch to using replaceAllUsesWith() to replace the prototype-less function uses. This new approach results in some redundant bitcasting but is much simpler and handles all cases. Differential Revision: https://reviews.llvm.org/D56938 llvm-svn: 352445
* [WebAssembly] Expand BUILD_PAIR nodesThomas Lively2019-01-281-0/+33
| | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57276 llvm-svn: 352442
* Recommit r352255 "[SelectionDAG][X86] Don't use SEXTLOAD for promoting ↵Craig Topper2019-01-281-4/+4
| | | | | | | | | | | | | | | | masked loads in the type legalizer" This did not cause the buildbot failure it was previously reverted for. Original commit message: I'm not sure why we were using SEXTLOAD. EXTLOAD seems more appropriate since we don't care about the upper bits. This patch changes this and then modifies the X86 post legalization combine to emit a extending shuffle instead of a sign_extend_vector_inreg. Could maybe use an any_extend_vector_inre On AVX512 targets I think we might be able to use a masked vpmovzx and not have to expand this at all. llvm-svn: 352433
* [GlobalISel][AArch64] Add legalization for G_FLOGJessica Paquette2019-01-284-1/+258
| | | | | | | | | | This adds support for legalizing G_FLOG into a RTLib call. It adds a legalizer test, and updates the existing floating point tests. https://reviews.llvm.org/D57347 llvm-svn: 352429
* AMDGPU: Add DS append/consume intrinsicsMatt Arsenault2019-01-282-0/+250
| | | | | | | | | | | | | | | Since these pass the pointer in m0 unlike other DS instructions, these need to worry about whether the address is uniform or not. This assumes the address is dynamically uniform, and just uses readfirstlane to get a copy into an SGPR. I don't know if these have the same 16-bit add for the addressing mode offset problem on SI or not, but I've just assumed they do. Also includes some misc. changes to avoid test differences between the LDS and GDS versions. llvm-svn: 352422
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log10Jessica Paquette2019-01-284-1/+260
| | | | | | | | | | This adds instruction selection support for @llvm.log10 in AArch64. It teaches GISel to lower it to a library call, updates the relevant tests, and adds a legalizer test for log10. https://reviews.llvm.org/D57341 llvm-svn: 352418
* [AArch64] Add 'apple-latest' CPU aliasFrancis Visoiu Mistrih2019-01-282-0/+8
| | | | | | | | | | | | | | The 'apple-latest' alias is supposed to provide a CPU that contains the latest Apple processor model supported by LLVM. This is supposed to be used by tools like lldb to provide a target that supports most of the CPU features. For now, this is mapped to Cyclone. Differential Revision: https://reviews.llvm.org/D56384 llvm-svn: 352412
* [GlobalISel] Add ISel support for @llvm.lifetime.start and @llvm.lifetime.endJessica Paquette2019-01-284-0/+68
| | | | | | | | | | | | | | | | | | This adds ISel support for lifetime markers in opt levels above O0. It also updates the arm64-irtranslator test, and updates some AArch64 tests that use them for added coverage. It also adds a testcase taken from the X86 codegen tests which verified a bug caused by lifetime markers + stack colouring in the past. This is intended to make sure that GISel doesn't re-introduce the bug. (This is basically a straight copy from what SelectionDAG does in SelectionDAGBuilder.cpp) https://reviews.llvm.org/D57187 llvm-svn: 352410
* [CodeGen][X86] Expand UADDSAT to NOT+UMIN+ADDNikita Popov2019-01-282-1620/+854
| | | | | | | | | Followup to D56636, this time handling the UADDSAT case by expanding uadd.sat(a, b) to umin(a, ~b) + b. Differential Revision: https://reviews.llvm.org/D56869 llvm-svn: 352409
* [GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSINJessica Paquette2019-01-286-6/+548
| | | | | | | | | | | | This contains all of the legalizer changes from D57197 necessary to select G_FCOS and G_FSIN. It also updates several existing IR tests in test/CodeGen/AArch64 that verify that we correctly lower the G_FCOS and G_FSIN instructions. https://reviews.llvm.org/D57197 3/3 llvm-svn: 352402
* [GlobalISel][AArch64] Add IRTranslator support for G_FCOS and G_FSINJessica Paquette2019-01-281-0/+16
| | | | | | | | | This adds IRTranslator support for the G_FCOS and G_FSIN generic instructions. https://reviews.llvm.org/D57197 2/3 llvm-svn: 352401
* [GlobalISel] Add G_FSIN and G_FCOS generic instructionsJessica Paquette2019-01-281-1/+7
| | | | | | | | | | This introduces generic instrutions for floating point sin and cos, G_FCOS and G_FSIN. It updates the tests, etc. https://reviews.llvm.org/D57197 1/3 llvm-svn: 352400
* [X86][AVX] Remove lowerShuffleByMerging128BitLanes 2-lane restrictionSimon Pilgrim2019-01-281-17/+7
| | | | | | | | First step towards adding support for 64-bit unary "sublane" handling (a bit like lowerShuffleAsRepeatedMaskAndLanePermute). This allows us to add lowerV64I8Shuffle handling. llvm-svn: 352389
* [x86] allow more shuffle splitting to avoid vpermps (PR40434)Sanjay Patel2019-01-282-104/+37
| | | | | | | | | | | | | | | This is tricky to make optimal: sometimes we're better off using a single wider op, but other times it makes more sense to combine a narrow ops to achieve the same result. This solves the case from: https://bugs.llvm.org/show_bug.cgi?id=40434 There's potentially a similar change for vectors with 64-bit elements, but it needs adjustments similar to rL352333 to avoid creating infinite loops. llvm-svn: 352380
* [mips] Support for +abs2008 attributeAleksandar Beserminji2019-01-283-21/+86
| | | | | | | | | | | | | | | | Instruction abs.[ds] is not generating correct result when working with NaNs for revisions prior mips32r6 and mips64r6. To generate a sequence which always produce a correct result, but also to allow user more control on how his code is compiled, attribute +abs2008 is added, so user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Differential Revision: https://reviews.llvm.org/D35983 llvm-svn: 352370
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-281-0/+187
| | | | | | | | | | | | | | | | | | | Summary: Added the intrinsics llvm.amdgcn.interp.p1.f16() and llvm.amdgcn.interp.p2.f16() and related LIT test. The p1 intrinsic generates code appropriate for both 16 and 32 bank LDS. Reviewers: #amdgpu, dstuttard, arsenm, tpr Reviewed By: #amdgpu, arsenm Subscribers: jvesely, mgorny, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46754 llvm-svn: 352357
* [MIPS GlobalISel] Select subPetar Avramovic2019-01-284-0/+561
| | | | | | | | | Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
* [ARM GlobalISel] Support integer division for Thumb2Diana Picus2019-01-282-39/+124
| | | | | | | | | Support G_SDIV, G_UDIV, G_SREM and G_UREM. The only significant difference between arm and thumb mode is that we need to check a different subtarget feature. llvm-svn: 352346
* [X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types ↵Craig Topper2019-01-288-341/+2022
| | | | | | | | for the mask argument. Remove and autoupgrade the old intrinsics llvm-svn: 352343
* [X86] Add vbmi2 compressstore and expandload tests that aren't fast-isel tests.Craig Topper2019-01-283-92/+666
| | | | | | | | These got removed when we autoupgraded to target independent intrinsics, but we didn't have coverage anywhere else. The avx512f/avx512vl versions do have coverage. Also move some tests back from the upgrade file that aren't really upgraded. llvm-svn: 352342
* [AArch64][GlobalISel] Teach RBS about G_FNEG default mapping.Amara Emerson2019-01-281-0/+14
| | | | llvm-svn: 352340
* [AArch64][GlobalISel] Add some missing vector support for FP arithmetic ops.Amara Emerson2019-01-284-33/+107
| | | | | | | Moved the fneg lowering legalization test from AArch64 to X86, as we want to specify that it's already legal. llvm-svn: 352338
* [AArch64][GlobalISel] Add some vector support for fp <-> int conversions.Amara Emerson2019-01-283-10/+154
| | | | | | Some unrelated, but benign, test changes as well due to the test update script. llvm-svn: 352337
* GlobalISel: Don't reduce elements for atomic load/storeMatt Arsenault2019-01-271-0/+46
| | | | | | | This is invalid for the same reason as in the narrowScalar handling for load. llvm-svn: 352334
* [x86] add restriction for lowering to vpermpsSanjay Patel2019-01-271-58/+26
| | | | | | | | | This transform was added with rL351346, and we had an escape for shufps, but we also want one for unpckps vs. vpermps because vpermps doesn't take an immediate shuffle index operand. llvm-svn: 352333
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