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| author | Amara Emerson <aemerson@apple.com> | 2019-01-29 21:19:33 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-01-29 21:19:33 +0000 |
| commit | 102c9ed768d534189bb51b53212dbba7eee9e412 (patch) | |
| tree | 805e54caaa3524ce8d346b04eccdaaa951c684d2 /llvm/test/CodeGen | |
| parent | a4c33ecd78b3b8e3ceca3e6c96626218304110f5 (diff) | |
| download | bcm5719-llvm-102c9ed768d534189bb51b53212dbba7eee9e412.tar.gz bcm5719-llvm-102c9ed768d534189bb51b53212dbba7eee9e412.zip | |
[AArch64][GlobalISel] Unmerge into scalars from a vector should use FPR bank.
This currently shows up as a selection fallback since the dest regs were given
GPR banks but the source was a vector FPR reg.
Differential Revision: https://reviews.llvm.org/D57408
llvm-svn: 352545
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir new file mode 100644 index 00000000000..3123de27c1e --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir @@ -0,0 +1,26 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s +--- +name: unmerge +alignment: 2 +legalized: true +tracksRegLiveness: true +frameInfo: + maxCallFrameSize: 0 +body: | + bb.0: + liveins: $q0 + + ; Ensure that the dest regs have FPR since we're unmerging from a vector + ; CHECK-LABEL: name: unmerge + ; CHECK: liveins: $q0 + ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0 + ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) + ; CHECK: $x0 = COPY [[UV]](s64) + ; CHECK: RET_ReallyLR implicit $x0 + %0:_(<2 x s64>) = COPY $q0 + %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(<2 x s64>) + $x0 = COPY %1(s64) + RET_ReallyLR implicit $x0 + +... |
