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* [X86][SSE] Dropped -mcpu from bitcast+setcc mask testsSimon Pilgrim2017-07-052-130/+130
| | | | | | Use triple and attribute only for consistency llvm-svn: 307176
* [Power9] Exploit vector extract with variable index.Tony Jiang2017-07-051-0/+167
| | | | | | | | | | | | | | | | This patch adds the exploitation for new power 9 instructions which extract variable elements from vectors: VEXTUBLX VEXTUBRX VEXTUHLX VEXTUHRX VEXTUWLX VEXTUWRX Differential Revision: https://reviews.llvm.org/D34032 Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) llvm-svn: 307174
* [Power9] Exploit vector integer extend instructions when indices aren't correct.Tony Jiang2017-07-051-28/+225
| | | | | | | | | | | | | | | This patch adds on to the exploitation added by https://reviews.llvm.org/D33510. This now catches build vector nodes where the inputs are coming from sign extended vector extract elements where the indices used by the vector extract are not correct. We can still use the new hardware instructions by adding a shuffle to move the elements to the correct indices. I introduced a new PPCISD node here because adding a vector_shuffle and changing the elements of the vector_extracts was getting undone by another DAG combine. Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) Differential Revision: https://reviews.llvm.org/D34009 llvm-svn: 307169
* [Hexagon] Preclude non-memory test from being optimized away. NFC.Nirav Dave2017-07-0511-38/+38
| | | | llvm-svn: 307153
* [GlobalIsel] allow x86_fp80 values to be dumped.Igor Breger2017-07-051-0/+18
| | | | | | | | | | | | | | | | Summary: Otherwise the fallback path fails with an assertion on x86_64 targets, when "x86_fp80" is encountered. Reviewers: t.p.northover, zvi, guyblank Reviewed By: zvi Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34975 llvm-svn: 307140
* Add the missing triple to the test case added as part of r307120.Nemanja Ivanovic2017-07-051-1/+1
| | | | llvm-svn: 307122
* [PowerPC] Fix for PR33636Nemanja Ivanovic2017-07-051-0/+702
| | | | | | | | Remove casts to a constant when a node can be an undef. Differential Revision: https://reviews.llvm.org/D34808 llvm-svn: 307120
* Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffsetNirav Dave2017-07-058-210/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | Relanding after rewriting undef.ll test to avoid host-dependant endianness. As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using generic checks. Also, propagate missing local handling from there to BaseIndexOffset checks. Tests of note: * test/CodeGen/X86/build-vector* - Improved. * test/CodeGen/BPF/undef.ll - Improved store alignment allows an additional store merge * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a case we already do not handle well. Here, the DAG is improved, but scheduling causes a code size degradation. Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab Subscribers: nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D34472 llvm-svn: 307114
* Revert "[AVR] Add the branch selection pass from the GitHub repository"Dylan McKay2017-07-053-7/+7
| | | | | | This reverts commit 602ef067c1d58ecb425d061f35f2bc4c7e92f4f3. llvm-svn: 307111
* [AVR] Add the branch selection pass from the GitHub repositoryDylan McKay2017-07-053-7/+7
| | | | | | | We should rewrite this using the generic branch relaxation pass, but for the moment having this pass is better than hitting an assertion error. llvm-svn: 307109
* NFC.Gadi Haber2017-07-041-210/+835
| | | | | | | | | | | | | | | Made some updates to the half.ll test under CodeGen to make it friendly to the update_llc_test_checks .py tool as follows: 1.Removing the llc flag -asm-verbose=false 2.Grouping the multiple check-prefix directives 3.Apply update_llc_test_checks.py tool on the test This change is needed to easily update scheduling changes in an upcoming patch. Reviewers: zvi, RKSimon, craig.topper Differential Revision: https://reviews.llvm.org/D34934 llvm-svn: 307108
* [ARM][test] Added test/CodeGen/ARM/ror.ll test. NFC precommit for D12833.Andrew Zhogin2017-07-041-0/+36
| | | | llvm-svn: 307103
* [X86][SSE4A] Add support for combining from non-v16i8 EXTRQI/INSERTQI shufflesSimon Pilgrim2017-07-042-36/+41
| | | | | | With the improved shuffle decoding we can now combine EXTRQI/INSERTQI shuffles from non-v16i8 vector types llvm-svn: 307099
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-04141-559/+789
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307097
* [FastISel] Move gc intrinsic test to X86 directoryAnna Thomas2017-07-041-0/+2
| | | | | | | | | Move from generic to X86 directory since gc intrinsics only supposed in X86 64 bit. Add target triple as well. Fixes build failure in i686-linux-RA caused by rL307084. llvm-svn: 307086
* [FastISel][SelectionDAG]Teach fastISel about GC intrinsicsAnna Thomas2017-07-041-0/+55
| | | | | | | | | | | | | | | | | | | | | | | Summary: We are crashing in LLC at O0 when gc intrinsics are present in the block. The reason being FastISel performs basic block ISel by modifying GC.relocates to be the first instruction in the block. This can cause us to visit the GC relocate before it's corresponding GC.statepoint is visited, which is incorrect. When we lower the statepoint, we record the base and derived pointers, along with the gc.relocates. After this we can visit the gc.relocate. This patch avoids fastISel from incorrectly creating the block with gc.relocate as the first instruction. Reviewers: qcolombet, skatkov, qikon, reames Reviewed by: skatkov Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34421 llvm-svn: 307084
* [X86] Add combine tests for vector rotatesSimon Pilgrim2017-07-041-0/+83
| | | | | | Reference tests for D12833 llvm-svn: 307073
* NFC commit.Gadi Haber2017-07-041-25/+26
| | | | | | | | | | | | Converting the Codegen test "extractelement-legalization-store-ordering.ll" to be "update_llc_test_checks" friendly. The changes to the test are needed for an upcoming scheduling patch. Reviewers: zvi, RKSimon Differential Revision: https://reviews.llvm.org/D34935 llvm-svn: 307066
* [X86] Add comment string for broadcast loads from the constant pool.Craig Topper2017-07-046-639/+1459
| | | | | | | | | | | | | | | | | Summary: When broadcasting from the constant pool its useful to print out the final vector similar to what we do for normal moves from the constant pool. I changed only a couple tests that were broadcast focused. One of them had been previously hand tweaked after running the script so that it could check the constant pool declaration. But I think this patch makes that unnecessary now since we can check the comment instead. Reviewers: spatel, RKSimon, zvi Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34923 llvm-svn: 307062
* [AVR] Fix bug which caused assertion errors for some FRMIDX instructionsDylan McKay2017-07-041-0/+33
| | | | | | | | | | | | | Previously, if a basic block ended with a FRMIDX instruction, we would end up doing something like this. *std::next(MBB.end()) Which would hit an error: "Assertion `!NodePtr->isKnownSentinel()' failed." llvm-svn: 307057
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-04140-788/+558
| | | | | | | | | It broke a testcase. Failing Tests (1): LLVM :: CodeGen/AMDGPU/alignbit-pat.ll llvm-svn: 307054
* [legalize-types] Clean up softening machinery.Anton Yartsev2017-07-041-0/+55
| | | | | | | | The patch makes SoftenFloatResult/Operand logic just the same as all other legalization routines have: SoftenFloatResult() now fills the SoftenFloats map and SoftenFloatOperand() perform all needed replacements. This prevents softening mashinery from leaving stale entries in SoftenFloats map (that resulted in errors during the legalize type checking) and clarifies softening. The patch replaces https://reviews.llvm.org/D29265. Differential Revision: https://reviews.llvm.org/D31946 llvm-svn: 307053
* [X86][SSE4A] Add support for combining from EXTRQI/INSERTQI shufflesSimon Pilgrim2017-07-032-18/+9
| | | | llvm-svn: 307048
* [X86][SSE4A] Add SSE4A shuffle tests on pre-SSSE3 hardwareSimon Pilgrim2017-07-031-0/+71
| | | | llvm-svn: 307042
* [X86][SSE4A] Test SSE4A shuffle combining on SSE42 capable target as wellSimon Pilgrim2017-07-031-17/+36
| | | | llvm-svn: 307038
* DAGCombine: Combine BUILD_VECTOR to TRUNCATEZvi Rackover2017-07-033-557/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a combine for creating a truncate to replace a build_vector composed of extracts with indices that form a stride-2^N series. Example: v8i32 V = ... v4i32 build_vector((extract_elt V, 0), (extract_elt V, 2), (extract_elt V, 4), (extract_elt V, 6)) --> v4i32 truncate (bitcast V to v4i64) Related discussion in llvm-dev about canonicalizing shuffles to truncates in LLVM IR: http://lists.llvm.org/pipermail/llvm-dev/2017-January/108936.html. Reviewers: spatel, RKSimon, efriedma, igorb, craig.topper, wolfgangp, delena Reviewed By: delena Subscribers: guyblank, delena, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D34077 llvm-svn: 307036
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-034-155/+162
| | | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. There were also over-specifications in the RUN params such as CPU model. llvm-svn: 307033
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-034-219/+539
| | | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. There were also several over-specifications in the RUN params such as CPU model or OS requirement llvm-svn: 307028
* [X86][SSE4A] Add tests showing missed opportunities to combine ↵Simon Pilgrim2017-07-031-0/+80
| | | | | | EXTRQI/INSERTQI shuffles llvm-svn: 307027
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-03140-558/+788
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307026
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-034-337/+337
| | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 307024
* [GlobalISel][X86] fix %ptr(p0) = G_CONSTANT selection.Igor Breger2017-07-032-0/+40
| | | | llvm-svn: 307019
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-021-0/+29
| | | | llvm-svn: 306995
* [X86][AVX512] Test AVX512VPOPCNTDQ CTPOP with/without AVX512BWSimon Pilgrim2017-07-021-29/+57
| | | | llvm-svn: 306991
* [X86][AVX512VPOPCNTDQ] Improve support for v16i8/v8i16/v16i16/ CTPOPSimon Pilgrim2017-07-026-156/+111
| | | | | | Zero extend to v16i32/v8i64, use VPOPCNTDQ instructions and truncate back. llvm-svn: 306990
* [X86][AVX512] Cleanup tzcnt tests triples and attributesSimon Pilgrim2017-07-021-36/+36
| | | | | | Avoid use of specific -mcpu llvm-svn: 306989
* [X86][AVX512] Cleanup popcnt tests triples and attributesSimon Pilgrim2017-07-021-15/+15
| | | | | | Avoid use of specific -mcpu llvm-svn: 306988
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-024-72/+126
| | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 306984
* [x86] remove unnecessary RUN for test after auto-generating checks; NFCSanjay Patel2017-07-021-5/+21
| | | | llvm-svn: 306983
* [x86] update test to use FileCheck and auto-generate checks; NFCSanjay Patel2017-07-021-1/+50
| | | | llvm-svn: 306982
* [x86] auto-generate complete checks for tests; NFCSanjay Patel2017-07-024-32/+41
| | | | | | These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 306981
* [X86][SSE] Attempt to combine 64-bit and 32-bit shuffles to unary shuffles ↵Simon Pilgrim2017-07-022-2/+2
| | | | | | | | before bit shifts We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive llvm-svn: 306978
* [X86][SSE] Attempt to combine 64-bit and 16-bit shuffles to unary shuffles ↵Simon Pilgrim2017-07-021-5/+2
| | | | | | | | | | before bit shifts We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive The 32-bit shuffles are a bit tricky and will be dealt with in a later patch llvm-svn: 306977
* [X86][SSE] Add test showing missed opportunity to combine to pshuflwSimon Pilgrim2017-07-021-0/+18
| | | | | | We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive llvm-svn: 306976
* [X86] Rerun "update_llc_test_checks" tool on CodeGen tests. NFC.Gadi Haber2017-07-023-0/+75
| | | | | | | | | | This is NFC after rerunning the "update_llc_test_checks.py" tool on the CodeGen X86 tests in order to submit a patch. Minor differences due to added "End of Function" lines. Reviewers: zvi Differential Revision: https://reviews.llvm.org/D34933 llvm-svn: 306973
* [GlobalISel][X86] Support G_GLOBAL_VALUE operation.Igor Breger2017-07-024-0/+220
| | | | | | | | | | | | | | | | | Summary: Support G_GLOBAL_VALUE operation. For now most of the PIC configurations not implemented yet. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34738 Conflicts: test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir llvm-svn: 306972
* [GlobalISel][X86] Support vector type G_UNMERGE_VALUES selection.Igor Breger2017-07-023-17/+283
| | | | | | | | | | | | | | | | Summary: Support vector type G_UNMERGE_VALUES selection. For now G_UNMERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Reviewers: t.p.northover, qcolombet, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33665 llvm-svn: 306971
* fix trivial typos; NFCHiroshi Inoue2017-07-021-1/+1
| | | | | | suport -> support llvm-svn: 306968
* [X86][RDSEED] Split off i64 intrinsic tests and test i16/i32 on 32-bit ↵Simon Pilgrim2017-07-012-29/+56
| | | | | | target as well. llvm-svn: 306961
* [X86][RDRAND] Split off i64 intrinsic tests and test i16/i32 on 32-bit ↵Simon Pilgrim2017-07-012-36/+102
| | | | | | target as well. llvm-svn: 306960
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