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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-02 23:21:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-07-02 23:21:48 +0000 |
| commit | 3f031e75aaa9579de41e45dcdc0e22a6cdb96f13 (patch) | |
| tree | aab62d27a11bb31b68e1e3e1786320b0b70148ba /llvm/test/CodeGen | |
| parent | f05c5ef44197057742fc1143ddfdcb8b6fc516af (diff) | |
| download | bcm5719-llvm-3f031e75aaa9579de41e45dcdc0e22a6cdb96f13.tar.gz bcm5719-llvm-3f031e75aaa9579de41e45dcdc0e22a6cdb96f13.zip | |
AMDGPU: Add operand target flags serialization
llvm-svn: 306995
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir new file mode 100644 index 00000000000..7d288dd1b04 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir @@ -0,0 +1,29 @@ +# RUN: llc -march=amdgcn -run-pass none -o - %s | FileCheck %s +--- | + define amdgpu_kernel void @flags() { + ret void + } + + declare void @foo() +... +--- + +# CHECK: SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc +# CHECK: %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo + +name: flags +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + maxAlignment: 8 +registers: + - { id: 0, class: sreg_64, preferred-register: '' } + - { id: 1, class: sreg_64, preferred-register: '' } +body: | + bb.0: + liveins: %sgpr0_sgpr1 + %0 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @foo + 4, target-flags(amdgpu-rel32-hi) @foo + 4, implicit-def dead %scc + %1 = S_MOV_B64 target-flags(amdgpu-gotprel) @foo + + S_ENDPGM +... |
