summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen
diff options
context:
space:
mode:
authorIgor Breger <igor.breger@intel.com>2017-07-03 11:06:54 +0000
committerIgor Breger <igor.breger@intel.com>2017-07-03 11:06:54 +0000
commit5c787ab346c3517f987d7f872a9e653d74d7a5df (patch)
tree162e49bfdfe11eeb550af47de85d4e4bd78bb9e5 /llvm/test/CodeGen
parent9bf0e0362f2a1f431e56f8e313fb924ac083e16d (diff)
downloadbcm5719-llvm-5c787ab346c3517f987d7f872a9e653d74d7a5df.tar.gz
bcm5719-llvm-5c787ab346c3517f987d7f872a9e653d74d7a5df.zip
[GlobalISel][X86] fix %ptr(p0) = G_CONSTANT selection.
llvm-svn: 307019
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/GlobalISel/constant.ll9
-rw-r--r--llvm/test/CodeGen/X86/GlobalISel/select-constant.mir31
2 files changed, 40 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/constant.ll b/llvm/test/CodeGen/X86/GlobalISel/constant.ll
index b550bb0bc7b..5b512f9ce93 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/constant.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/constant.ll
@@ -51,4 +51,13 @@ define i64 @const_i64_i32() {
ret i64 -1
}
+define void @main(i32 ** %data) {
+; ALL-LABEL: main:
+; ALL: # BB#0:
+; ALL-NEXT: movq $0, %rax
+; ALL-NEXT: movq %rax, (%rdi)
+; ALL-NEXT: retq
+ store i32* null, i32** %data, align 8
+ ret void
+}
diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
index 4b91b5f9f09..30f57418b4c 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir
@@ -29,6 +29,11 @@
ret i64 -1
}
+ define void @main(i32** %data) {
+ store i32* null, i32** %data, align 8
+ ret void
+ }
+
...
---
name: const_i8
@@ -162,3 +167,29 @@ body: |
RET 0, implicit %rax
...
+---
+name: main
+# CHECK-LABEL: name: main
+alignment: 4
+legalized: true
+regBankSelected: true
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT: - { id: 1, class: gr64, preferred-register: '' }
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+# CHECK: %0 = COPY %rdi
+# CHECK-NEXT: %1 = MOV64ri32 0
+# CHECK-NEXT: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.data)
+# CHECK-NEXT: RET 0
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %rdi
+
+ %0(p0) = COPY %rdi
+ %1(p0) = G_CONSTANT i64 0
+ G_STORE %1(p0), %0(p0) :: (store 8 into %ir.data)
+ RET 0
+
+...
OpenPOWER on IntegriCloud