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authorSanjay Patel <spatel@rotateright.com>2017-07-02 14:50:35 +0000
committerSanjay Patel <spatel@rotateright.com>2017-07-02 14:50:35 +0000
commit27cccc96c2b373ae6a5593145051ccf614c2ade5 (patch)
tree7efd53e26da5420fdc6cb2c83f4367b5bb5c3bdc /llvm/test/CodeGen
parentc3d5cf0bb71f4278ae2e489cefbbe031522e97b3 (diff)
downloadbcm5719-llvm-27cccc96c2b373ae6a5593145051ccf614c2ade5.tar.gz
bcm5719-llvm-27cccc96c2b373ae6a5593145051ccf614c2ade5.zip
[x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 306981
Diffstat (limited to 'llvm/test/CodeGen')
-rw-r--r--llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll15
-rw-r--r--llvm/test/CodeGen/X86/x32-lea-1.ll10
-rw-r--r--llvm/test/CodeGen/X86/zext-shl.ll39
-rw-r--r--llvm/test/CodeGen/X86/zext-trunc.ll9
4 files changed, 41 insertions, 32 deletions
diff --git a/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll b/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
index 1c352782fca..745316effc9 100644
--- a/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
+++ b/llvm/test/CodeGen/X86/vec_unsafe-fp-math.ll
@@ -1,13 +1,13 @@
-; RUN: llc < %s -enable-unsafe-fp-math -enable-no-signed-zeros-fp-math -mtriple=x86_64-unknown-unknown -mcpu=corei7 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -enable-unsafe-fp-math -enable-no-signed-zeros-fp-math -mtriple=x86_64-unknown-unknown | FileCheck %s
; Make sure that vectors get the same benefits as scalars when using unsafe-fp-math.
; Subtracting zero is free.
define <4 x float> @vec_fsub_zero(<4 x float> %x) {
; CHECK-LABEL: vec_fsub_zero:
-; CHECK-NOT: subps
-; CHECK-NOT: xorps
-; CHECK: retq
+; CHECK: # BB#0:
+; CHECK-NEXT: retq
%sub = fsub <4 x float> %x, zeroinitializer
ret <4 x float> %sub
}
@@ -15,9 +15,10 @@ define <4 x float> @vec_fsub_zero(<4 x float> %x) {
; Negating doesn't require subtraction.
define <4 x float> @vec_fneg(<4 x float> %x) {
; CHECK-LABEL: vec_fneg:
-; CHECK: xorps {{.*}}LCP{{.*}}, %xmm0
-; CHECK-NOT: subps
-; CHECK-NEXT: retq
+; CHECK: # BB#0:
+; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: retq
%sub = fsub <4 x float> zeroinitializer, %x
ret <4 x float> %sub
}
+
diff --git a/llvm/test/CodeGen/X86/x32-lea-1.ll b/llvm/test/CodeGen/X86/x32-lea-1.ll
index 2f7d71e2baf..afe3581a85b 100644
--- a/llvm/test/CodeGen/X86/x32-lea-1.ll
+++ b/llvm/test/CodeGen/X86/x32-lea-1.ll
@@ -1,10 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -O0 | FileCheck %s
-; CHECK: leal {{[-0-9]*}}(%r{{s|b}}p),
-; CHECK-NOT: leal {{[-0-9]*}}(%e{{s|b}}p),
define void @foo(i32** %p) {
+; CHECK-LABEL: foo:
+; CHECK: # BB#0:
+; CHECK-NEXT: leal -{{[0-9]+}}(%rsp), %eax
+; CHECK-NEXT: addl $16, %eax
+; CHECK-NEXT: movl %eax, (%edi)
+; CHECK-NEXT: retq
%a = alloca i32, i32 10
%addr = getelementptr i32, i32* %a, i32 4
store i32* %addr, i32** %p
ret void
}
+
diff --git a/llvm/test/CodeGen/X86/zext-shl.ll b/llvm/test/CodeGen/X86/zext-shl.ll
index ac3ecc85f2d..7722f46d753 100644
--- a/llvm/test/CodeGen/X86/zext-shl.ll
+++ b/llvm/test/CodeGen/X86/zext-shl.ll
@@ -1,25 +1,26 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s
-define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
-entry:
+define i32 @t1(i8 zeroext %x) nounwind {
; CHECK-LABEL: t1:
-; CHECK: shll
-; CHECK-NOT: movzwl
-; CHECK: ret
- %0 = zext i8 %x to i16
- %1 = shl i16 %0, 5
- %2 = zext i16 %1 to i32
- ret i32 %2
+; CHECK: # BB#0:
+; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: shll $5, %eax
+; CHECK-NEXT: retl
+ %t0 = zext i8 %x to i16
+ %t1 = shl i16 %t0, 5
+ %t2 = zext i16 %t1 to i32
+ ret i32 %t2
}
-define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
-entry:
+define i32 @t2(i8 zeroext %x) nounwind {
; CHECK-LABEL: t2:
-; CHECK: shrl
-; CHECK-NOT: movzwl
-; CHECK: ret
- %0 = zext i8 %x to i16
- %1 = lshr i16 %0, 3
- %2 = zext i16 %1 to i32
- ret i32 %2
+; CHECK: # BB#0:
+; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT: shrl $3, %eax
+; CHECK-NEXT: retl
+ %t0 = zext i8 %x to i16
+ %t1 = lshr i16 %t0, 3
+ %t2 = zext i16 %t1 to i32
+ ret i32 %t2
}
diff --git a/llvm/test/CodeGen/X86/zext-trunc.ll b/llvm/test/CodeGen/X86/zext-trunc.ll
index 32afd6b96a8..e51a77abc92 100644
--- a/llvm/test/CodeGen/X86/zext-trunc.ll
+++ b/llvm/test/CodeGen/X86/zext-trunc.ll
@@ -1,11 +1,12 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; rdar://7570931
define i64 @foo(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: foo:
-; CHECK: leal
-; CHECK-NOT: movl
-; CHECK: ret
+; CHECK: # BB#0:
+; CHECK-NEXT: leal (%rdi,%rsi), %eax
+; CHECK-NEXT: retq
%c = add i64 %a, %b
%d = trunc i64 %c to i32
%e = zext i32 %d to i64
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