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* [X86][MMX] Fixed i32 extraction on 32-bit targetsSimon Pilgrim2017-03-021-21/+6
| | | | | | MMX extraction often ends up as extract_i32(bitcast_v2i32(extract_i64(bitcast_v1i64(x86mmx v), 0)), 0) which fails to simplify on 32-bit targets as i64 isn't legal llvm-svn: 296782
* [X86][SSE] Attempt to extract vector elements through target shufflesSimon Pilgrim2017-02-271-9/+3
| | | | | | | | | | DAGCombiner already supports peeking thorough shuffles to improve vector element extraction, but legalization often leaves us in situations where we need to extract vector elements after shuffles have already been lowered. This patch adds support for VECTOR_EXTRACT_ELEMENT/PEXTRW/PEXTRB instructions to attempt to handle target shuffles as well. I've covered some basic scenarios including handling shuffle mask scaling and the implicit zero-extension of PEXTRW/PEXTRB, there is more that could be done here (that I've mentioned in TODOs) but I haven't found many cases where its worth it. Differential Revision: https://reviews.llvm.org/D30176 llvm-svn: 296381
* [X86][SSE] Propagate undef upper elements from scalar_to_vector during ↵Simon Pilgrim2017-02-151-1/+1
| | | | | | | | shuffle combining Only do this for integer types currently - floats types (in particular insertps) load folding often fails with this. llvm-svn: 295208
* [X86][SSE] Add support for combining target shuffles to SHUFPS.Simon Pilgrim2016-12-181-8/+8
| | | | | | As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point. llvm-svn: 290064
* [X86][SSE] Fix domains for VZEXT_LOAD type instructionsSimon Pilgrim2016-12-151-4/+4
| | | | | | | | Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions. Differential Revision: https://reviews.llvm.org/D27684 llvm-svn: 289825
* [X86] Don't assume that MMX extractelts are from index 0.Ahmed Bougacha2016-04-271-0/+28
| | | | | | | It's probably the case for all 3 MMX users out there, but with hand-crafted IR, you can trigger selection failures. Fix that. llvm-svn: 267652
* [X86] Re-enable MMX i32 extractelt combine.Ahmed Bougacha2016-04-271-0/+15
| | | | | | | | | This effectively adds back the extractelt combine removed by r262358: the direct case can still occur (because x86_mmx is special, see r262446), but it's the indirect case that's now superseded by the generic combine. llvm-svn: 267651
* [X86][SSE] Regenerated the vec_extract tests.Simon Pilgrim2016-04-011-23/+81
| | | | llvm-svn: 265183
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* [X86][MMX] Fix a typo in a couple of testsBruno Cardoso Lopes2015-02-261-1/+1
| | | | llvm-svn: 230638
* [X86][MMX] Remove widening experimental flag from MMX tests.Bruno Cardoso Lopes2015-02-261-7/+8
| | | | | | | | Turns out that after the past MMX commits, we don't need to rely on this flag to get better codegen for MMX. Also update the tests to become triple neutral. llvm-svn: 230637
* [X86][MMX] Reapply: Add MMX instructions to foldable tablesBruno Cardoso Lopes2015-02-251-2/+1
| | | | | | | | | | Reapply r230248. Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230499
* Revert "[X86][MMX] Add MMX instructions to foldable tables"Bruno Cardoso Lopes2015-02-231-2/+4
| | | | | | This reverts commit r230226 since it breaks win buildbots. llvm-svn: 230248
* [X86][MMX] Add MMX instructions to foldable tablesBruno Cardoso Lopes2015-02-231-4/+2
| | | | | | | | Teach the peephole optimizer to work with MMX instructions by adding entries into the foldable tables. This covers folding opportunities not handled during isel. llvm-svn: 230226
* [X86][MMX] Handle i32->mmx conversion using movdBruno Cardoso Lopes2015-02-051-3/+2
| | | | | | | | | Implement a BITCAST dag combine to transform i32->mmx conversion patterns into a X86 specific node (MMX_MOVW2D) and guarantee that moves between i32 and x86mmx are better handled, i.e., don't use store-load to do the conversion.. llvm-svn: 228293
* [X86][MMX] Improve transfer from mmx to i32Bruno Cardoso Lopes2015-02-031-7/+4
| | | | | | | | | | | | | Improve EXTRACT_VECTOR_ELT DAG combine to catch conversion patterns between x86mmx and i32 with more layers of indirection. Before: movq2dq %mm0, %xmm0 movd %xmm0, %eax After: movd %mm0, %eax llvm-svn: 227969
* [X86][MMX] Add tests for MMX extract elementBruno Cardoso Lopes2015-02-021-0/+75
LLVM ToT produces poor MMX code compared to 3.5. However, part of the previous functionality can be achieved by using -x86-experimental-vector-widening-legalization. Add tests to be sure we don't regress again. llvm-svn: 227869
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