[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794

1 files changed, 3 insertions, 3 deletions

diff --git a/llvm/test/CodeGen/X86/vec_extract-mmx.ll b/llvm/test/CodeGen/X86/vec_extract-mmx.ll
index c6c93a11d6d..780066d2da1 100644
--- a/llvm/test/CodeGen/X86/vec_extract-mmx.ll
+++ b/llvm/test/CodeGen/X86/vec_extract-mmx.ll
@@ -8,7 +8,7 @@ define i32 @test0(<1 x i64>* %v4) {
 ; CHECK-NEXT:    addl $32, %eax
 ; CHECK-NEXT:    retq
 entry:
-  %v5 = load <1 x i64>* %v4, align 8
+  %v5 = load <1 x i64>, <1 x i64>* %v4, align 8
   %v12 = bitcast <1 x i64> %v5 to <4 x i16>
   %v13 = bitcast <4 x i16> %v12 to x86_mmx
   %v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
@@ -30,7 +30,7 @@ define i32 @test1(i32* nocapture readonly %ptr) {
 ; CHECK-NEXT:    emms
 ; CHECK-NEXT:    retq
 entry:
-  %0 = load i32* %ptr, align 4
+  %0 = load i32, i32* %ptr, align 4
   %1 = insertelement <2 x i32> undef, i32 %0, i32 0
   %2 = insertelement <2 x i32> %1, i32 0, i32 1
   %3 = bitcast <2 x i32> %2 to x86_mmx
@@ -56,7 +56,7 @@ define i32 @test2(i32* nocapture readonly %ptr) {
 ; CHECK-NEXT:    retq
 entry:
   %0 = bitcast i32* %ptr to x86_mmx*
-  %1 = load x86_mmx* %0, align 8
+  %1 = load x86_mmx, x86_mmx* %0, align 8
   %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
   %3 = bitcast x86_mmx %2 to <4 x i16>
   %4 = bitcast <4 x i16> %3 to <1 x i64>