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* Revert r356996 "[DAG] Avoid smart constructor-based dangling nodes."Nirav Dave2019-03-271-6/+4
| | | | | | | This patch appears to trigger very large compile time increases in halide builds. llvm-svn: 357116
* [DAG] Avoid smart constructor-based dangling nodes.Nirav Dave2019-03-261-4/+6
| | | | | | | | | | | | | | | Various SelectionDAG non-combine operations (e.g. the getNode smart constructor and legalization) may leave dangling nodes by applying optimizations or not fully pruning unused result values. This can result in nodes that are never added to the worklist and therefore can not be pruned. Add a node inserter as the current node deleter to make sure such nodes have the chance of being pruned. Many minor changes, mostly positive. llvm-svn: 356996
* [DAGCombiner] When combining zero_extend of a truncate, only mask before ↵Craig Topper2018-03-011-0/+1
| | | | | | | | | | extending for vectors. Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code. Differential Revision: https://reviews.llvm.org/D42679 llvm-svn: 326500
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-4/+4
| | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
* [X86] Add an override of targetShrinkDemandedConstant to limit the damage ↵Craig Topper2018-01-201-4/+6
| | | | | | | | | | | | | | | | | | | that shrinkdemandedbits can do to zext_in_reg operations Summary: This patch adds an implementation of targetShrinkDemandedConstant that tries to keep shrinkdemandedbits from removing bits that would otherwise have been recognized as a movzx. We still need a follow patch to stop moving ands across srl if the and could be represented as a movzx before the shift but not after. I think this should help with some of the cases that D42088 ended up removing during isel. Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42265 llvm-svn: 323048
* [x86] regenerate complete checks; NFCSanjay Patel2018-01-191-30/+51
| | | | | | D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
* Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier ↵Stephen Lin2013-07-131-5/+5
| | | | | | | | | | debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
* reapply: Use the new TB_NOT_REVERSABLE flag instead of specialChris Lattner2010-10-081-2/+36
| | | | | | | | | reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
* Revert "reimplement the second half of the or/add optimization. We should now",Daniel Dunbar2010-10-081-36/+2
| | | | | | which depends on r116007, which I am about to revert. llvm-svn: 116031
* reimplement the second half of the or/add optimization. We should nowChris Lattner2010-10-081-2/+36
| | | | | | | | | | only end up emitting LEA instead of OR. If we aren't able to promote something into an LEA, we should never be emitting it as an ADD. Add some testcases that we emit "or" in cases where we used to produce an "add". llvm-svn: 116026
* Extend r93152 to work on OR r, r. If the source set bits are known not to ↵Evan Cheng2010-01-111-0/+16
| | | | | | overlap, then select as an ADD instead. llvm-svn: 93191
* Select an OR with immediate as an ADD if the input bits are known zero. This ↵Evan Cheng2010-01-111-0/+11
allow the instruction to be 3address-fied if needed. llvm-svn: 93152
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