Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.

llvm-svn: 93152

1 files changed, 11 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/3addr-or.ll b/llvm/test/CodeGen/X86/3addr-or.ll
new file mode 100644
index 00000000000..395ba46aab3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/3addr-or.ll
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; rdar://7527734
+
+define i32 @test(i32 %x) nounwind readnone ssp {
+entry:
+; CHECK: test:
+; CHECK: leal 3(%rdi), %eax
+  %0 = shl i32 %x, 5                              ; <i32> [#uses=1]
+  %1 = or i32 %0, 3                               ; <i32> [#uses=1]
+  ret i32 %1
+}