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* [SystemZ] Use VGM whenever possible to load FP immediates.Jonas Paulsson2019-02-122-1/+64
| | | | | | | | | | | | | isFPImmLegal() has been extended to recognize certain FP immediates that can be built with VGM (Vector Generate Mask). These scalar FP immediates (that were previously loaded from the constant pool) are now selected as VGMF/VGMG in Select(). Review: Ulrich Weigand https://reviews.llvm.org/D58003 llvm-svn: 353867
* [SystemZ] Improved handling of the @llvm.ctlz intrinsic.Jonas Paulsson2019-02-061-0/+107
| | | | | | | | | | | | | | Since SystemZ supports counting of leading zeros with the FLOGR instruction, isCheapToSpeculateCtlz() should return true, which it now does. ISD::CTLZ_ZERO_UNDEF i32 is now handled the same way as ISD::CTLZ is, which is needed since promotion to i64 is required and CTLZ_ZERO_UNDEF is only expanded to CTLZ if it is Legal or Custom. Review: Ulrich Weigand https://reviews.llvm.org/D57710 llvm-svn: 353330
* [SystemZ] Wait with VGBM selection until after DAGCombine2.Jonas Paulsson2019-02-063-78/+55
| | | | | | | | | | | | | | | | | Don't lower BUILD_VECTORs to BYTE_MASK, but instead expose the BUILD_VECTORs to the DAGCombiner and select them to VGBM in Select(). This allows the DAGCombiner to understand the constant vector values. For floating point, only all-zeros vectors are now generated with VGBM, as it turned out to be somewhat complicated to handle any arbitrary constants, while in practice this is very rare and hardly needed. The SystemZ ISD opcodes z_byte_mask, z_vzero and z_vones have been removed. Review: Ulrich Weigand https://reviews.llvm.org/D57152 llvm-svn: 353325
* [SystemZ] Do not return INT_MIN from strcmp/memcmpUlrich Weigand2019-02-062-38/+38
| | | | | | | | | | | | | | | | | | | The IPM sequence currently generated to compute the strcmp/memcmp result will return INT_MIN for the "less than zero" case. While this is in compliance with the standard, strictly speaking, it turns out that common applications cannot handle this, e.g. because they negate a comparison result in order to implement reverse compares. This patch changes code to use a different sequence that will result in -2 for the "less than zero" case (same as GCC). However, this requires that the two source operands of the compare instructions are inverted, which breaks the optimization in removeIPMBasedCompare. Therefore, I've removed this (and all of optimizeCompareInstr), and replaced it with a mostly equivalent optimization in combineCCMask at the DAGcombine level. llvm-svn: 353304
* [CodeGenPrepare] Handle all debug calls in dupRetToEnableTailCallOpts()Jonas Paulsson2019-01-291-0/+171
| | | | | | | | | | | | This patch makes sure that a debug value that is after the bitcast in dupRetToEnableTailCallOpts() is also skipped. The reduced test case is from SPEC-2006 on SystemZ. Review: Vedant Kumar, Wolfgang Pieb https://reviews.llvm.org/D57050 llvm-svn: 352462
* [SystemZ] Remember to reset the NoPHIs property on MF in createPHIsForSelects()Jonas Paulsson2019-01-241-2/+2
| | | | | | | | After creating new PHI instructions during isel pseudo expansion, the NoPHIs property of MF should be reset in case it was previously set. Review: Ulrich Weigand llvm-svn: 352030
* [SystemZ] Fix test case for buildbot.Jonas Paulsson2019-01-231-2/+2
| | | | | | | | | | llvm-clang-x86_64-expensive-checks-win triggered this assert: "llvm.dbg.value intrinsic requires a !dbg attachment" Hopefully, adding reasonable !dbg operands solves this. llvm-svn: 351939
* [SystemZ] Handle DBG_VALUE instructions in two places in backend.Jonas Paulsson2019-01-233-0/+258
| | | | | | | | | | | | | | | | | Two backend optimizations failed to handle cases when compiled with -g, due to failing to consider DBG_VALUE instructions. This was in SystemZTargetLowering::emitSelect() and SystemZElimCompare::getRegReferences(). This patch makes sure that DBG_VALUEs are recognized so that they do not affect these optimizations. Tests for branch-on-count, load-and-trap and consecutive selects. Review: Ulrich Weigand https://reviews.llvm.org/D57048 llvm-svn: 351928
* Remove irrelevant references to legacy git repositories fromJames Y Knight2019-01-154-4/+4
| | | | | | | | | compiler identification lines in test-cases. (Doing so only because it's then easier to search for references which are actually important and need fixing.) llvm-svn: 351200
* Replace "no-frame-pointer-*" function attributes with "frame-pointer"Francis Visoiu Mistrih2019-01-146-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
* Pythran compat - range vs. xrangeSerge Guelton2019-01-0312-34/+34
| | | | | | | | | Use range instead of xrange whenever possible. The extra list creation in Python2 is generally not a performance bottleneck. Differential Revision: https://reviews.llvm.org/D56253 llvm-svn: 350309
* Python compat - print statementSerge Guelton2019-01-0314-307/+337
| | | | | | | | | Make sure all print statements are compatible with Python 2 and Python3 using the `from __future__ import print_function` statement. Differential Revision: https://reviews.llvm.org/D56249 llvm-svn: 350307
* [SystemZ] Make better use of VLLEZUlrich Weigand2018-12-202-0/+54
| | | | | | | | | | | | | | | | This patch fixes two deficiencies in current code that recognizes the VLLEZ idiom: - For the floating-point versions, we have ISel patterns that match on a bitconvert as the top node. In more complex cases, that bitconvert may already have been merged into something else. Fix the patterns to match the inner nodes instead. - For the 64-bit integer versions, depending on the surrounding code, we may get either a DAG tree based on JOIN_DWORDS or one based on INSERT_VECTOR_ELT. Use a PatFrags to simply match both variants. llvm-svn: 349749
* [SystemZ] Make better use of VGEF/VGEGUlrich Weigand2018-12-201-0/+32
| | | | | | | | | Current code in SystemZDAGToDAGISel::tryGather refuses to perform any transformation if the Load SDNode has more than one use. This (erronously) counts uses of the chain result, which prevents the optimization in many cases unnecessarily. Fixed by this patch. llvm-svn: 349748
* [SystemZ] Make better use of VLDEBUlrich Weigand2018-12-201-3/+14
| | | | | | | | | | | We already have special code (DAG combine support for FP_ROUND) to recognize cases where we an use a vector version of VLEDB to perform two floating-point truncates in parallel, but equivalent support for VLEDB (vector floating-point extends) has been missing so far. This patch adds corresponding DAG combine support for FP_EXTEND. llvm-svn: 349746
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-9/+10
| | | | | | Differential Revision: https://reviews.llvm.org/D55600 llvm-svn: 349264
* [SystemZ] make test immune to scalarization improvements; NFCSanjay Patel2018-12-141-1/+4
| | | | | | | The undef operands mean this test is probably still too fragile to accomplish what the comments suggest. llvm-svn: 349164
* [SystemZ] Pass copy-hinted regs first from getRegAllocationHints().Jonas Paulsson2018-12-131-0/+280
| | | | | | | | | When computing register allocation hints for a GRX32Bit register, make sure that any of the hinted registers that are also copy hints are returned first in the list. Review: Ulrich Weigand. llvm-svn: 349037
* [TargetLowering] Add ISD::AND handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-121-13/+9
| | | | | | | | If either of the operand elements are zero then we know the result element is going to be zero (even if the other element is undef). Differential Revision: https://reviews.llvm.org/D55558 llvm-svn: 348926
* Regenerate knownbits test. NFCI.Simon Pilgrim2018-12-121-13/+27
| | | | | | A future SimplifyDemandedBits patch will affect this code and I want to ensure the codegen diff is obvious. llvm-svn: 348925
* [Targets] Fixup incorrect targets in codemodel testsDavid Green2018-12-101-2/+2
| | | | llvm-svn: 348796
* [Targets] Add errors for tiny and kernel codemodel on targets that don't ↵David Green2018-12-071-0/+9
| | | | | | | | | | | support them Adds fatal errors for any target that does not support the Tiny or Kernel codemodels by rejigging the getEffectiveCodeModel calls. Differential Revision: https://reviews.llvm.org/D50141 llvm-svn: 348585
* [SystemZ] make test immune to improvements in undef simplificationSanjay Patel2018-11-181-2/+2
| | | | llvm-svn: 347166
* DAG combiner: fold (select, C, X, undef) -> XStanislav Mekhanoshin2018-11-161-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D54646 llvm-svn: 347110
* [SystemZ] Increase the number of VLREPsJonas Paulsson2018-11-132-0/+71
| | | | | | | | | | | | | | | If a loaded value is replicated it is best to combine these two operations into a VLREP (load and replicate), but isel will not produce this if the load has other users as well. This patch handles this by putting the other users of the load to use the REPLICATE 0-element instead of the load. This way the load has only the REPLICATE node as user, and we get a VLREP. Review: Ulrich Weigand https://reviews.llvm.org/D54264 llvm-svn: 346746
* [SystemZ] Replicate the load with most uses in buildVector()Jonas Paulsson2018-11-121-0/+19
| | | | | | | | | | | Iterate over all elements and count the number of uses among them for each used load. Then make sure to REPLICATE the load which has the most uses in order to minimize the number of needed element insertions. Review: Ulrich Weigand https://reviews.llvm.org/D54322 llvm-svn: 346637
* [SystemZ] Add a couple of missing testsUlrich Weigand2018-11-091-10/+55
| | | | | | | | | | | A few fp128 tests were omitted from test/CodeGen/SystemZ/fp-round-01.ll since in early days, LLVM couldn't handle implicitly generated library calls to functions with long double arguments on SystemZ. This deficiency was actually long since fixed, but those tests are still missing. This patch adds the missing tests. NFC. llvm-svn: 346541
* [SystemZ] Avoid inserting same value after replicationJonas Paulsson2018-11-091-0/+20
| | | | | | | | | | | A minor improvement of buildVector() that skips creating an INSERT_VECTOR_ELT for a Value which has already been used for the REPLICATE. Review: Ulrich Weigand https://reviews.llvm.org/D54315 llvm-svn: 346504
* [DAGCombine] Improve alias analysis for chain of independent stores.Nirav Dave2018-11-081-42/+27
| | | | | | | | | | | | | | | | | | | FindBetterNeighborChains simulateanously improves the chain dependencies of a chain of related stores avoiding the generation of extra token factors. For chains longer than the GatherAllAliasDepths, stores further down in the chain will necessarily fail, a potentially significant waste and preventing otherwise trivial parallelization. This patch directly parallelize the chains of stores before improving each store. This generally improves DAG-level parallelism. Reviewers: courbet, spatel, RKSimon, bogner, efriedma, craig.topper, rnk Subscribers: sdardis, javed.absar, hiraditya, jrtc27, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D53552 llvm-svn: 346432
* [SystemZ] Bugfix in shouldCoalesce()Jonas Paulsson2018-11-081-0/+68
| | | | | | | | | | | | | | | | | | | | It was discovered in randomized testing that the SystemZ implementation of shouldCoalesce() could be caused to crash when subreg liveness was enabled. This was because an undef use of the virtual register was copied outside current MBB at the point of shouldCoalesce() being called. For more details, see https://bugs.llvm.org/show_bug.cgi?id=39276. This patch changes the check for MBB locality from livein/liveout checks to do checks for all instructions of both intervals being inside MBB. This avoids the cases with dead defs / undef uses outside MBB, which are not affecting liveness in/out of MBB. The original test case included as a reduced .mir test case. Review: Ulrich Weigand https://reviews.llvm.org/D54197 llvm-svn: 346406
* [SchedModel] Fix for read advance cycles with implicit pseudo operands.Jonas Paulsson2018-10-301-0/+31
| | | | | | | | | | | | | | | | | | The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 llvm-svn: 345606
* Relax fast register allocator related test cases; NFCMatthias Braun2018-10-292-10/+6
| | | | | | | | | | | | | - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
* Regenerate FP_TO_INT tests.Simon Pilgrim2018-10-272-30/+84
| | | | | | Precursor to fix for PR17686 llvm-svn: 345453
* [SystemZ] Pass the DAG pointer from SystemZAddressingMode::dump().Jonas Paulsson2018-10-261-1/+1
| | | | | | | | | | | | | In order to print the IR slot number for the memory operand, the DAG pointer must be passed to SDNode::dump(). The isel-debug.ll test updated to also check for the IR Value reference being printed correctly. Review: Ulrich Weigand https://reviews.llvm.org/D53333 llvm-svn: 345347
* Fix in MachineOperand::printIRValueReference().Jonas Paulsson2018-10-251-0/+19
| | | | | | | | | | | Handle the case where getCurrentFunction() returns nullptr by passing -1 to printIRSlotNumber(). This will result in <badref> being printed instead of an assertion failure. Review: Francis Visoiu Mistrih https://reviews.llvm.org/D53333 llvm-svn: 345342
* [NFC] Rename minnan and maxnan to minimum and maximumThomas Lively2018-10-242-6/+6
| | | | | | | | | | | | | | | Summary: Changes all uses of minnan/maxnan to minimum/maximum globally. These names emphasize that the semantic difference between these operations is more than just NaN-propagation. Reviewers: arsenm, aheejin, dschuff, javed.absar Subscribers: jholewinski, sdardis, wdng, sbc100, jgravelle-google, jrtc27, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D53112 llvm-svn: 345218
* [DAGCombine] Improve Load-Store ForwardingNirav Dave2018-10-101-2/+1
| | | | | | | | | | | | | | | | | | Summary: Extend analysis forwarding loads from preceeding stores to work with extended loads and truncated stores to the same address so long as the load is fully subsumed by the store. Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are deleted as they've no longer seem to be relevant. Reviewers: RKSimon, rnk, kparzysz, javed.absar Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D49200 llvm-svn: 344142
* [DAGCombiner] Add X / X -> 1 & X % X -> 0 folds (test tweaks)Simon Pilgrim2018-08-291-4/+4
| | | | | | | | Adjust tests to avoid the X / X -> 1 & X % X -> 0 folds while keeping their original purposes. Differential Revision: https://reviews.llvm.org/D50636 llvm-svn: 340916
* [PPC] Remove Darwin support from POWER backend.Kit Barton2018-08-281-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch issues an error message if Darwin ABI is attempted with the PPC backend. It also cleans up existing test cases, either converting the test to use an alternative triple or removing the test if the coverage is no longer needed. Updated Tests ------------- The majority of test cases were updated to use a different triple that does not include the Darwin ABI. Many tests were also updated to use FileCheck, in place of grep. Deleted Tests ------------- llvm/test/tools/dsymutil/PowerPC/sibling.test was originally added to test specific functionality of dsymutil using an object file created with an old version of llvm-gcc for a Powerbook G4. After a discussion with @JDevlieghere he suggested removing the test. llvm/test/CodeGen/PowerPC/combine_loads_from_build_pair.ll was converted from a PPC test to a SystemZ test, as the behavior is also reproducible there. All other tests that were deleted were specific to the darwin/ppc ABI and no longer necessary. Phabricator Review: https://reviews.llvm.org/D50988 llvm-svn: 340795
* [RegisterCoalscer] Manually remove leftover segments when commuting defKrzysztof Parzyszek2018-08-211-0/+78
| | | | | | | | | | | | | In removeCopyByCommutingDef, segments from the source live range are copied into (and merged with) the segments of the target live range. This is performed for all subranges of the source interval. It can happen that there will be subranges of the target interval that had no corresponding subranges in the source interval, and in such cases these subrages will not be updated. Since the copy being coalesced is about to be removed, these ranges need to be updated by removing the segments that are started by the copy. llvm-svn: 340318
* [SystemZ] Require asserts in subregliveness-06.mirKrzysztof Parzyszek2018-08-161-0/+3
| | | | | | The option -misched=shuffle is only available with !NDEBUG builds. llvm-svn: 339931
* [MachineVerifier] Check if predecessor is jointly dominated by undefsKrzysztof Parzyszek2018-08-161-0/+272
| | | | | | | | Each use of a value should be jointly dominated by the union of defs and undefs. It can happen that it will only be jointly dominated by undefs, and that is still legal. Make sure that the verifier is aware of that. llvm-svn: 339924
* [RegisterCoalescer] Shrink to uses if needed after removeCopyByCommutingDefKrzysztof Parzyszek2018-08-161-0/+48
| | | | llvm-svn: 339912
* [RegisterCoalescer] Ensure that both registers have subranges if one doesKrzysztof Parzyszek2018-08-151-0/+41
| | | | llvm-svn: 339792
* [RegisterCoalescer] Reset VNInfo def when copying segments overKrzysztof Parzyszek2018-08-151-0/+51
| | | | llvm-svn: 339788
* [RegAlloc] Check that subreg liveness tracking applies to given virtual regKrzysztof Parzyszek2018-08-151-0/+22
| | | | | | | | Subregister liveness applies selectively to register classes with certain properties. Make sure that when it's enabled, it applies to a given virtual register (in virtual register rewriter). llvm-svn: 339784
* [SystemZ] Add testcase for r339778Krzysztof Parzyszek2018-08-151-0/+48
| | | | llvm-svn: 339780
* [SystemZ] Improve handling of instructions which expand to several groupsJonas Paulsson2018-08-031-0/+90
| | | | | | | | | | | Some instructions expand to more than one decoder group. This has been hitherto ignored, but is handled with this patch. Review: Ulrich Weigand https://reviews.llvm.org/D50187 llvm-svn: 338849
* [SystemZ, TableGen] Fix shift count handlingUlrich Weigand2018-08-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | The DAG combiner logic to simplify AND masks in shift counts is invalid. While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior). Instead, this patch performs equivalent operations during instruction selection. For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags. For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value. Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node. This patch also fixes that bug by simply recurring through the whole pattern. This should be NFC for all other targets. Differential Revision: https://reviews.llvm.org/D50096 llvm-svn: 338521
* [SystemZ] Improve decoding in case of instructions with four register operands.Jonas Paulsson2018-07-311-2/+2
| | | | | | | | | | | | | | Since z13, the max group size will be 2 if any μop has more than 3 register sources. This has been ignored sofar in the SystemZHazardRecognizer, but is now handled by recognizing those instructions and adjusting the tracking of decoding and the cost heuristic for grouping. Review: Ulrich Weigand https://reviews.llvm.org/D49847 llvm-svn: 338368
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