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| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2018-10-30 15:04:40 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2018-10-30 15:04:40 +0000 |
| commit | 611b533f1d544b85f1a98afbc9241deeb97d9497 (patch) | |
| tree | 4db26c1d883b521a32b55e1e3489edc8bd900fc2 /llvm/test/CodeGen/SystemZ | |
| parent | 023b1d19f3de5ed7cec535295bf0d7a9f99ea561 (diff) | |
| download | bcm5719-llvm-611b533f1d544b85f1a98afbc9241deeb97d9497.tar.gz bcm5719-llvm-611b533f1d544b85f1a98afbc9241deeb97d9497.zip | |
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
The SchedModel allows the addition of ReadAdvances to express that certain
operands of the instructions are needed at a later point than the others.
RegAlloc may add pseudo operands that are not part of the instruction
descriptor, and therefore cannot have any read advance entries. This meant
that in some cases the desired read advance was nullified by such a pseudo
operand, which still had the original latency.
This patch fixes this by making sure that such pseudo operands get a zero
latency during DAG construction.
Review: Matthias Braun, Ulrich Weigand.
https://reviews.llvm.org/D49671
llvm-svn: 345606
Diffstat (limited to 'llvm/test/CodeGen/SystemZ')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/misched-readadvances.mir | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/misched-readadvances.mir b/llvm/test/CodeGen/SystemZ/misched-readadvances.mir new file mode 100644 index 00000000000..df8ca2f5f95 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/misched-readadvances.mir @@ -0,0 +1,31 @@ +# Check that the extra operand for the full register added by RegAlloc does +# not have a latency that interferes with the latency adjustment +# (ReadAdvance) for the MSY register operand. + +# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=machine-scheduler \ +# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s +# REQUIRES: asserts + +# CHECK: ScheduleDAGMI::schedule starting +# CHECK: SU(4): renamable $r2l = MSR renamable $r2l(tied-def 0), renamable $r2l +# CHECK: Latency : 6 +# CHECK: SU(5): renamable $r2l = MSY renamable $r2l(tied-def 0), renamable $r1d, -4, $noreg, implicit $r2d +# CHECK: Predecessors: +# CHECK: SU(4): Data Latency=2 Reg=$r2l +# CHECK: SU(4): Data Latency=0 Reg=$r2d + +--- +name: Perl_do_sv_dump +alignment: 4 +tracksRegLiveness: true +body: | + bb.0 : + %1:addr64bit = IMPLICIT_DEF + %2:addr64bit = IMPLICIT_DEF + %3:vr64bit = IMPLICIT_DEF + + bb.1 : + %2:addr64bit = ALGFI %2, 4294967291, implicit-def dead $cc + %2.subreg_l32:addr64bit = MSR %2.subreg_l32, %2.subreg_l32 + %2.subreg_l32:addr64bit = MSY %2.subreg_l32, %1, -4, $noreg +... |
