Relax fast register allocator related test cases; NFC

- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
  of going through the whole codegen pipeline.

This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.

llvm-svn: 345532

2 files changed, 6 insertions, 10 deletions

diff --git a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
index 3956ce99623..195dbb996ef 100644
--- a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
+++ b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
@@ -13,22 +13,18 @@
 name:            main
 alignment:       2
 tracksRegLiveness: true
-registers:       
-  - { id: 0, class: gr128bit }
-  - { id: 1, class: gr64bit }
-  - { id: 2, class: addr64bit }
-# CHECK: $r0q = L128
-# CHECK-NEXT: $r0l = COPY renamable $r1l
+# CHECK: $r0l = COPY renamable $r1l
 # Although R0L partially redefines R0Q, it must not mark R0Q as kill
 # because R1D is still live through that instruction.
 # CHECK-NOT: implicit killed $r0q
-# CHECK-NEXT: $r2d = COPY renamable $r1d
+# CHECK-NEXT: {{\$r[0-9]+d}} = COPY renamable $r1d
 # CHECK-NEXT: LARL
 body:             |
   bb.0:
+    %0 : gr128bit = IMPLICIT_DEF
     %0.subreg_hl32 = COPY %0.subreg_l32
-    %1 = COPY %0.subreg_l64
-    %2 = LARL @g_167
+    %1 : gr64bit = COPY %0.subreg_l64
+    %2 : addr64bit = LARL @g_167
     STC %1.subreg_l32, %2, 8, $noreg
 
 ...
diff --git a/llvm/test/CodeGen/SystemZ/rosbg-02.ll b/llvm/test/CodeGen/SystemZ/rosbg-02.ll
index fa1ac6e75ea..8a7357a5318 100644
--- a/llvm/test/CodeGen/SystemZ/rosbg-02.ll
+++ b/llvm/test/CodeGen/SystemZ/rosbg-02.ll
@@ -18,7 +18,7 @@ define void @main() {
   %7 = zext i1 %6 to i32
   %8 = load i32, i32* @g_999, align 4
   %9 = or i32 %8, %7
-; CHECK: rosbg   %r1, %r3, 63, 63, 33
+; CHECK: rosbg   {{%r[0-9]+}}, {{%r[0-9]+}}, 63, 63, 33
   store i32 %9, i32* @g_999, align 4
   ret void
 }