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* [RISCV] Handle globals and block addresses in asm operandsLuís Marques2020-01-131-2/+44
| | | | | | | | | | Summary: These seem to be the machine operand types currently needed by the RISC-V target. Reviewers: asb, lenary Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D72275
* [RISCV] Fix a couple of tests' CHECKsLuis Marques2019-08-301-0/+29
| | | | llvm-svn: 370466
* [RISCV] Lower inline asm constraint A for RISC-VLewis Revill2019-08-161-0/+25
| | | | | | | | | | | | This allows arguments with the constraint A to be lowered to input nodes for RISC-V, which implies a memory address stored in a register. This patch adds the minimal amount of code required to get operands with the right constraints to compile. https://reviews.llvm.org/D54296 llvm-svn: 369095
* [RISCV] Support z and i operand modifiersAlex Bradbury2019-07-081-0/+45
| | | | | | | Differential Revision: https://reviews.llvm.org/D57792 Patch by James Clarke. llvm-svn: 365291
* [RISCV] Fix inline-asm.ll test by adding nounwind attributeAlex Bradbury2019-06-121-3/+3
| | | | | | This test failed since CFI directive support was added in r361320. llvm-svn: 363123
* [RISCV] Lower inline asm constraints I, J & K for RISC-VLewis Revill2019-06-111-0/+68
| | | | | | | | | | | | | This validates and lowers arguments to inline asm nodes which have the constraints I, J & K, with the following semantics (equivalent to GCC): I: Any 12-bit signed immediate. J: Immediate integer zero only. K: Any 5-bit unsigned immediate. Differential Revision: https://reviews.llvm.org/D54093 llvm-svn: 363054
* [RISCV][NFC] Add nounwind attribute to functions missing it in ↵Alex Bradbury2019-05-231-4/+4
| | | | | | | | test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
* [RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll testAlex Bradbury2019-02-141-0/+31
| | | | llvm-svn: 354028
* [RISCV] Peephole optimisation for load/store of global values or constant ↵Alex Bradbury2018-03-191-2/+1
| | | | | | | | | | | addresses (load (add base, off), 0) -> (load base, off) (store val, (add base, off)) -> (store val, base, off) This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG. llvm-svn: 327831
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-28/+0
| | | | llvm-svn: 322839
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+83
llvm-svn: 322217
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