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| author | Alex Bradbury <asb@lowrisc.org> | 2019-02-14 13:09:54 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2019-02-14 13:09:54 +0000 |
| commit | 4efa0b674d7082fd8a736bc5789097e4d4d9d41c (patch) | |
| tree | 0748918f44e8a67b5e9fc7820f9cd8a368d91781 /llvm/test/CodeGen/RISCV/inline-asm.ll | |
| parent | 458d1457fb51c4537c3404dfa4ecd615c0621709 (diff) | |
| download | bcm5719-llvm-4efa0b674d7082fd8a736bc5789097e4d4d9d41c.tar.gz bcm5719-llvm-4efa0b674d7082fd8a736bc5789097e4d4d9d41c.zip | |
[RISCV][NFC] Add RV64I CHECK lines to inline-asm.ll test
llvm-svn: 354028
Diffstat (limited to 'llvm/test/CodeGen/RISCV/inline-asm.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/inline-asm.ll | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll index a16375be692..f17852cff25 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I %s @gi = external global i32 @@ -13,6 +15,15 @@ define i32 @constraint_r(i32 %a) { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: #NO_APP ; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_r: +; RV64I: # %bb.0: +; RV64I-NEXT: lui a1, %hi(gi) +; RV64I-NEXT: lwu a1, %lo(gi)(a1) +; RV64I-NEXT: #APP +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret %1 = load i32, i32* @gi %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) ret i32 %2 @@ -25,6 +36,13 @@ define i32 @constraint_i(i32 %a) { ; RV32I-NEXT: addi a0, a0, 113 ; RV32I-NEXT: #NO_APP ; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_i: +; RV64I: # %bb.0: +; RV64I-NEXT: #APP +; RV64I-NEXT: addi a0, a0, 113 +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret %1 = load i32, i32* @gi %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113) ret i32 %2 @@ -36,6 +54,12 @@ define void @constraint_m(i32* %a) { ; RV32I-NEXT: #APP ; RV32I-NEXT: #NO_APP ; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_m: +; RV64I: # %bb.0: +; RV64I-NEXT: #APP +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret call void asm sideeffect "", "=*m"(i32* %a) ret void } @@ -47,6 +71,13 @@ define i32 @constraint_m2(i32* %a) { ; RV32I-NEXT: lw a0, 0(a0) ; RV32I-NEXT: #NO_APP ; RV32I-NEXT: ret +; +; RV64I-LABEL: constraint_m2: +; RV64I: # %bb.0: +; RV64I-NEXT: #APP +; RV64I-NEXT: lw a0, 0(a0) +; RV64I-NEXT: #NO_APP +; RV64I-NEXT: ret %1 = tail call i32 asm "lw $0, $1", "=r,*m"(i32* %a) nounwind ret i32 %1 } |
