| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -17/+0 |
| | | | | | llvm-svn: 239657 | ||||
| * | R600: Use function inputs to represent data stored in gpr | Vincent Lejeune | 2013-11-11 | 1 | -6/+7 |
| | | | | | llvm-svn: 194425 | ||||
| * | R600: Fix handling of NAN in comparison instructions | Tom Stellard | 2013-09-28 | 1 | -1/+1 |
| | | | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603 | ||||
| * | R600: Schedule copy from phys register at beginning of block | Vincent Lejeune | 2013-06-05 | 1 | -1/+1 |
| | | | | | | | It allows regalloc pass to remove them by trivially assigning associated reg llvm-svn: 183336 | ||||
| * | R600: use capital letter for PV channel | Vincent Lejeune | 2013-06-03 | 1 | -1/+1 |
| | | | | | llvm-svn: 183107 | ||||
| * | R600: Use bottom up scheduling algorithm | Vincent Lejeune | 2013-05-17 | 1 | -1/+1 |
| | | | | | llvm-svn: 182129 | ||||
| * | R600: Prettier asmPrint of Alu | Vincent Lejeune | 2013-05-02 | 1 | -1/+1 |
| | | | | | llvm-svn: 180956 | ||||
| * | Add R600 backend | Tom Stellard | 2012-12-11 | 1 | -0/+16 |
| A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915 | |||||

