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path: root/llvm/test/CodeGen/R600/fmax.ll
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* R600 -> AMDGPU renameTom Stellard2015-06-131-17/+0
| | | | llvm-svn: 239657
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-6/+7
| | | | llvm-svn: 194425
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-1/+1
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-051-1/+1
| | | | | | It allows regalloc pass to remove them by trivially assigning associated reg llvm-svn: 183336
* R600: use capital letter for PV channelVincent Lejeune2013-06-031-1/+1
| | | | llvm-svn: 183107
* R600: Use bottom up scheduling algorithmVincent Lejeune2013-05-171-1/+1
| | | | llvm-svn: 182129
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-021-1/+1
| | | | llvm-svn: 180956
* Add R600 backendTom Stellard2012-12-111-0/+16
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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