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* R600 -> AMDGPU renameTom Stellard2015-06-13400-45283/+0
| | | | llvm-svn: 239657
* R600/SI: Add assembler support for FLAT instructionsTom Stellard2015-06-121-1/+1
| | | | | | | | - Add glc, slc, and tfe operands to flat instructions - Add missing flat instructions - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3. llvm-svn: 239637
* Don't depend on the interleaving of stdout and stderr.Rafael Espindola2015-06-121-9/+26
| | | | | | That can change as we change the buffering. llvm-svn: 239602
* Revert "Fix merges of non-zero vector stores"Reid Kleckner2015-06-111-10/+2
| | | | | | | | This reverts commit r239539. It was causing SDAG assertions while building freetype. llvm-svn: 239543
* Fix merges of non-zero vector storesMatt Arsenault2015-06-111-2/+10
| | | | | | | | | | Now actually stores the non-zero constant instead of 0. I somehow forgot to include this part of r238108. The test change was just an independent instruction order swap, so just add another check line to satisfy CHECK-NEXT. llvm-svn: 239539
* R600/SI: Add -mcpu=bonaire to a test that uses flat address spaceTom Stellard2015-06-111-1/+1
| | | | | | | Flat instructions don't exist on SI, but there is a bug in the backend that allows them to be selected. llvm-svn: 239533
* Implement computeKnownBits for min/max nodesMatt Arsenault2015-06-093-4/+103
| | | | llvm-svn: 239378
* DAGCombiner: don't duplicate (fmul x, c) in visitFNEG if fneg is freeFiona Glaser2015-06-051-0/+16
| | | | | | | | | | For targets with a free fneg, this fold is always a net loss if it ends up duplicating the multiply, so definitely avoid it. This might be true for some targets without a free fneg too, but I'll leave that for future investigation. llvm-svn: 239167
* R600/SI: Reimplement isLegalAddressingModeMatt Arsenault2015-06-041-0/+242
| | | | | | | | | | | Now that we sometimes know the address space, this can theoretically do a better job. This needs better test coverage, but this mostly depends on first updating the loop optimizatiosn to provide the address space. llvm-svn: 239053
* R600/SI: Fix some cases for load / store of halfMatt Arsenault2015-06-042-40/+559
| | | | | | | Mostly argument loads were producing broken zextloads from an FP type. llvm-svn: 239049
* R600: Re-enable sub-reg livenessTom Stellard2015-06-043-37/+4
| | | | | | The bug in the R600 backend that this uncovered has been fixed. llvm-svn: 238999
* R600/SI: Fix tests with triples in themMatt Arsenault2015-06-038-31/+10
| | | | | | | | Only set the triple from the command line options. Some of these were still testing SI features and using the old r600-- triple. llvm-svn: 238958
* LiveRangeEdit: Fix liveranges not shrinking on subrange kill.Matthias Braun2015-06-011-0/+55
| | | | | | | | | | | | | | If a dead instruction we may not only have a last-use in the main live range but also in a subregister range if subregisters are tracked. We need to partially rebuild live ranges in both cases. The testcase only broke when subregister liveness was enabled. I commited it in the current form because there is currently no flag to enable/disable subregister liveness. This fixes PR23720. llvm-svn: 238785
* R600: Use SIGN_EXTEND_INREG for SEXT loadsJan Vesely2015-05-261-70/+39
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com> llvm-svn: 238229
* R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chipsTom Stellard2015-05-251-8/+37
| | | | | | The src and dst register cannot be the same on chips with 16 lds banks. llvm-svn: 238147
* Add target hook to allow merging stores of nonzero constantsMatt Arsenault2015-05-242-2/+537
| | | | | | | | | | On GPU targets, materializing constants is cheap and stores are expensive, so only doing this for zero vectors was silly. Most of the new testcases aren't optimally merged, and are for later improvements. llvm-svn: 238108
* R600/SI: add pass to mark CF live ranges as non-spillableTom Stellard2015-05-121-0/+501
| | | | | | | | | | | | | | | | | | | | | | Spilling can insert instructions almost anywhere, and this can mess up control flow lowering in a multitude of ways, due to instruction reordering. Let's sort this out the easy way: never spill registers involved with control flow, i.e. saved EXEC masks. Unfortunately, this does not work at all with optimizations disabled, as the register allocator ignores spill weights. This should be addressed in a future commit. The test was reduced from the "stacks" shader of [1]. Some issues trigger the machine verifier while another one is checked manually. [1] http://madebyevan.com/webgl-path-tracing/ v2: only insert pass with optimizations enabled, merge test runs. Patch by: Grigori Goronzy llvm-svn: 237152
* R600/SI: Remove M0Reg register classTom Stellard2015-05-121-1/+1
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-122-2/+2
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* R600/SI: Make sendmsg test more strictTom Stellard2015-05-121-0/+2
| | | | | | We want to make sure that the m0 copies are being cse'd. llvm-svn: 237134
* R600/SI: Add VCC as an implict def of SI_KILLTom Stellard2015-05-011-0/+16
| | | | | | When SI_KILL has a register operand, its lowered form writes to vcc. llvm-svn: 236307
* R600/SI: Fix verifier errors from the SIAnnotateControlFlow passTom Stellard2015-05-011-0/+38
| | | | | | | | | | | | | This pass was generating 'Instruction does not dominate all uses!' errors for programs which had loops with a condition variable that depended on the result of a phi instruction from outside of the loop. The pass was inserting new phi nodes outside of the loop which used values defined inside the loop. http://bugs.freedesktop.org/show_bug.cgi?id=90056 llvm-svn: 236306
* Reinstate revisions r234755, r234759, r234760Jan Vesely2015-04-304-10/+74
| | | | | | | | | changes: Don't apply on hexagon and NVPTX since they no longer claim to support UADDO/USUBO Add location to getConstant Drop comment about the ops being turned into expand llvm-svn: 236240
* R600: Fix up for AsmPrinter's OutStreamer being a unique_ptrTom Stellard2015-04-281-0/+10
| | | | | | | | | | | Fixes a crash with basically any OpenGL application using the radeonsi driver. Patch by: Michel Dänzer Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90176 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 236004
* R600: Remove / merge redundant testcasesMatt Arsenault2015-04-263-43/+12
| | | | llvm-svn: 235813
* R600/SI: Fix verifier error when producing v_madmk_f32Matt Arsenault2015-04-241-0/+24
| | | | | | Copy the kill flags when swapping the operands. llvm-svn: 235687
* R600/RegisterCoalescer: Enable more rematerialization/add missing testcaseMatthias Braun2015-04-241-0/+57
| | | | | | | This enables the rematerialization of some R600 MOV instructions in the RegisterCoalescer and adds a testcase for r235668. llvm-svn: 235675
* R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operandsTom Stellard2015-04-231-0/+11
| | | | llvm-svn: 235662
* R600/SI: Fix indirect addressing with a negative constant offsetTom Stellard2015-04-231-0/+72
| | | | | | | | | | | When the base register index of the vector plus the constant offset was less than zero, we were passing the wrong base register to the indirect addressing instruction. In this case, we need to set the base register to v0 and then add the computed (negative) index to m0. llvm-svn: 235641
* R600: Fix always inline pass breaking noinline functionsMatt Arsenault2015-04-221-10/+9
| | | | | | No test since calls are not actually supported yet. llvm-svn: 235524
* DAGCombine: Remove redundant NaN checks around ISD::FSQRTTom Stellard2015-04-201-0/+50
| | | | | | | | This folds: (select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x) llvm-svn: 235333
* R600/SI: Fix verifier error caused by SIAnnotateControlFlowTom Stellard2015-04-141-0/+25
| | | | | | | | | | | | | | This pass will always try to insert llvm.SI.ifbreak intrinsics in the same block that its conditional value is computed in. This is a problem when conditions for breaks or continue are computed outside of the loop, because the llvm.SI.ifbreak intrinsic ends up being inserted outside of the loop. This patch fixes this problem by inserting the llvm.SI.ifbreak intrinsics in the loop header when the condition is computed outside the loop. llvm-svn: 234891
* Revert revisions r234755, r234759, r234760Jan Vesely2015-04-134-74/+10
| | | | | | | | | | | Revert "Remove default in fully-covered switch (to fix Clang -Werror -Wcovered-switch-default)" Revert "R600: Add carry and borrow instructions. Use them to implement UADDO/USUBO" Revert "LegalizeDAG: Try to use Overflow operations when expanding ADD/SUB" Using overflow operations fails CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll on hexagon, nvptx, and r600. Revert while I investigate. llvm-svn: 234768
* R600: Add carry and borrow instructions. Use them to implement UADDO/USUBOJan Vesely2015-04-134-8/+74
| | | | | | | | | | | | | | | | v2: tighten the sub64 tests v3: rename to CARRY/BORROW v4: fixup test cmdline add known bits computation use sign extend instead of sub 0,x better add test v5: remove redundant break move lowering to separate functions fix comments Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewers: arsenm llvm-svn: 234759
* LegalizeDAG: Try to use Overflow operations when expanding ADD/SUBJan Vesely2015-04-131-6/+4
| | | | | | | | | | v2: consider BooleanContents when processing overflow Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewers: resistor, jholewinsky (nvidia parts) Differential Revision: http://reviews.llvm.org/D6340 llvm-svn: 234755
* llvm/test/CodeGen/R600/fminnum.ll: Relax an expression for NaN on MSVCRT ↵NAKAMURA Takumi2015-04-131-1/+1
| | | | | | | | | like r204118. <stdin>:202:2: note: possible intended match here 2143289344(1.#QNAN0e+00), 2(2.802597e-45) llvm-svn: 234719
* R600: Make FMIN/MAXNUM legal on all asicsJan Vesely2015-04-122-0/+182
| | | | | | | | v2: Add tests Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234716
* R600/SI: Don't print offset0/offset1 DS operands when they are 0Tom Stellard2015-04-086-37/+37
| | | | llvm-svn: 234379
* [R600/SI] Fix testcase check line.Ahmed Bougacha2015-03-271-1/+1
| | | | | | Missing colon, instruction typo. llvm-svn: 233414
* Complete the MachineScheduler fix made way back in r210390.Andrew Trick2015-03-272-3/+3
| | | | | | | | | | | | | | | | | | "Fix the MachineScheduler's logic for updating ready times for in-order. Now the scheduler updates a node's ready time as soon as it is scheduled, before releasing dependent nodes." This fix was only made in one variant of the ScheduleDAGMI driver. Francois de Ferriere reported the issue in the other bit of code where it was also needed. I never got around to coming up with a test case, but it's an obvious fix that shouldn't be delayed any longer. I'll try to refactor this code a little better. I did verify performance on a wide variety of targets and saw no negative impact with this fix. llvm-svn: 233366
* R600/SI: Select V_BFE_U32 for and+shift with a non-literal offsetMarek Olsak2015-03-242-2/+10
| | | | llvm-svn: 233079
* R600/SI: Custom-select 32-bit S_BFE from bitwise opcodesMarek Olsak2015-03-243-19/+55
| | | | llvm-svn: 233078
* R600/SI: Improve BFM supportMarek Olsak2015-03-241-4/+23
| | | | llvm-svn: 233077
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-242-21/+102
| | | | | | | Other f64 opcodes not supported on SI can be lowered in a similar way. v2: use complex VOP3 patterns llvm-svn: 233076
* R600/SI: Expand fract to floor, then only select V_FRACT on CIMarek Olsak2015-03-241-5/+42
| | | | | | | | | V_FRACT is buggy on SI. R600-specific code is left intact. v2: drop the multiclass, use complex VOP3 patterns llvm-svn: 233075
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-2315-54/+751
| | | | | | | | | | | | | | | | | This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. llvm-svn: 232988
* R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2015-03-231-2/+33
| | | | | | | This function assumed that SMRD instructions always have immediate offsets, which is not always the case. llvm-svn: 232957
* R600: Cleanup test with multiple check prefixesMatt Arsenault2015-03-211-42/+40
| | | | llvm-svn: 232901
* R600/SI: Add missing CHECK-LABEL lines to a testTom Stellard2015-03-201-4/+4
| | | | llvm-svn: 232797
* Teach getDefaultFormat that we only support ELF on some architectures.Rafael Espindola2015-03-181-0/+3
| | | | | | | | | This should bring the windows bots back. It is a bit ugly, but it is better than what we had before: The triple would say that the object format was COFF, but llc/llvm-mc would produce an ELF. llvm-svn: 232683
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