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path: root/llvm/test/CodeGen/PowerPC/setcc-logic.ll
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* [PowerPC] Use xxleqv to set all one vector IMM(-1).Jinsong Ji2019-08-151-4/+4
* [DAGCombiner] convert logic-of-setcc into bit magic (PR40611)Sanjay Patel2019-02-121-10/+10
* [PowerPC] add tests for logic of setcc (PR40611); NFCSanjay Patel2019-02-121-0/+30
* [DAGCombiner] use root SDLoc for all nodes created by logic foldSanjay Patel2018-12-071-4/+4
* [PowerPC] Replace the Post RA List Scheduler with the Machine SchedulerStefan Pintilie2018-07-041-3/+3
* [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
* [PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic2017-12-151-2/+2
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-36/+36
* [PowerPC] Recommit r314244 with refactoring and off by defaultNemanja Ivanovic2017-11-301-6/+5
* [PowerPC] Reverting sequence of patches for elimination of comparison instruc...Nemanja Ivanovic2017-09-261-0/+1
* [PowerPC] Eliminate integer compare instructions - vol. 3Nemanja Ivanovic2017-06-071-7/+9
* [PowerPC] Eliminate integer compare instructions - vol. 1Nemanja Ivanovic2017-05-111-6/+6
* [DAGCombiner] add and use TLI hook to convert and-of-seteq / or-of-setne to b...Sanjay Patel2017-04-051-10/+11
* add/move codegen tests for and/or of setcc; NFCSanjay Patel2017-04-031-0/+62
* [DAGCombiner] enable vector transforms for any/all {sign} bits set/clearSanjay Patel2017-04-011-20/+10
* [PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFCSanjay Patel2017-04-011-0/+116
* [DAGCombiner] add fold for 'All sign bits set?'Sanjay Patel2017-03-311-9/+5
* [PowerPC] add tests for setcc+setcc+logic; NFCSanjay Patel2017-03-311-0/+313
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